Synchronous Down Counter - Lecture Notes | MCDB 152, Study notes of Neurobiology

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Synchronous Down Counter Make a synchronous down counter that counts down from 3 to 0 and takes in synchronous reset, enable, load, and data. Reset takes precedence over all other inputs, and upon reset the counter should go to 0. Upon load, the FSM goes to whatever state is on the input data. If neither load or reset is high, the FSM goes to the next state on positive clock edge if enable is high. Otherwise it stays in its current state. eo’ Sala EGR : | Siew st, Be n= eee \sae G) / canter?) (> / we a CO fe Q) voce > A omen rs Yo vere Rercke s oe - \aok module DownCounter(Reset, Load, Enable, Data, Count, clk); input Reset, Load, Enable, clk; input [1:0]Data; output [1:0]Count; reg [1:0]Count; always @(posedge clk} begin if{Reset) Count <= 0; else if(Load) Count <= Data; else if(Enable && Count==0 ) Count <= 3; else if(Enable) Count <= Count - 1; end endmodule