System Design Flow and Fixed-point Arithmetic (Lecture 3), Slides of Digital Systems Design

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System Design Flow and

Fixed-point Arithmetic

Lecture 3

Dr. Shoab A. Khan

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan

Contents

2

 Floating and Fixed Point Arithmetic

 System Design Flow

 Requirements and Specifications (R&S)

 Algorithmic Development in Matlab and Coding

Guidelines

 2’s Complement Arithmetic

 Floating Point Format

 Qn.m format for Fixed Point Arithmetic

 Addition, Multiplication and Scaling in Qn.m

 LTI systems and implementation in Qn.m format

System-level Design Flow and Fixed-point Arithmetic 4 Algorithm exploration and implementation in Floating Point Fixed Point Conversion System Integration Gate Level Net List Functional Verifiction Timing & Functional Verification Fixed Point Implementation S/W S/W H/W S/W or H/W Co-verification S/W or H/W Partition Synthesis RTL Verilog Implementation Requirements and Specifications Layout

System Design Flow

5

 The requirements and specifications of the application are captured

 The algorithms are then developed in double precision floating point format

 Matlab or C/C++

 A signal processing system general consists of hybrid target technologies

 DSPs, FPGAs, ASICs

 For mapping application developed in double precision is partitioned into

 hardware & software

 Most of signal processing applications are mapped on Fixed-point Digital

Signal Processors or HW in ASICs or FPGAs

 The HW and SW components of the application are converted into

Fixed Point format for this mapping

R&S of a UHF Radio (Cont)

7 Characteristic Specification Frequency range 420 MHz to 512 MHz Data rate Up to 512 kbps multi-channel non-line of sight Channel Multi-path with 15 μs delay spread and 220 km/h relative speed between transmitter and receiver Modulation OFDM supporting BPSK, QPSK and QAM FEC Turbo codes, convolution, Reed–Solomon Frequency hopping > 600 hops/s, frequency hopping on full hopping band Waveforms Radio works as SDR and should be capable of accepting additional waveforms

Next Step: Algorithm Development and Mapping 8

 The R&S related to digital design are forwarded to algorithm

developers and system designers

 Algorithms are coded in behavioral modeling tools like Matlab

 The Matlab code is then translated into a high level language,

for example, C/C++

 System is designed based on R&S

 System usually consists of hybrid technologies consisting of ASICs, DSPs, GPP, and FPGAs

 Partitioning of the application into HW/SW parts is performed

 The SW is then developed for the SW part and architectures

are designed and implemented for the HW parts

 Integration and testing is performed throughout the design

cycle

Processing in Chunks

10 % BPSK = 1, QPSK = 2, 8PSK = 3, 16QAM = 4 % All-user defined parameters are set in structure USER_PARAMS USER_PARAMS.MOD_SCH = 2; %select QPSK for current simulation USER_PARAMS.CHUNK_SZ = 256; %set buffer size USER_PARAMS.NO_CHUNKS = 100;% set no of chunks for simulation % generate raw data for simulation raw_data = randint(1, USER_PARAMS.NO_CHUNKSUSER_PARAMS.CHUNK_SZ) % Initialize user defined, system defined parameters and states PARAMS = MOD_Params_Init(USER_PARAMS); STATES = MOD_States_Init(PARAMS); mod_out = []; % Code should be structured to process data on chunk-by-chunk basis for iter = 0:USER_PARAMS.NO_CHUNKS- 1 in_data = raw_data (iterUSER_PARAMS.CHUNK_SZ+1:USER_PARAMS.CHUNK_SZ*(iter+1)); [out_sig,STATES]= Modulator(in_data,PARAMS,STATES); mod_out = [mod_out out_sig]; end

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan

Parameters & Initialization

11 % Initializing the user defined parameters and system design parameters in PARAMS function PARAMS = MOD_Params_Init(USER_PARAMS) % Structure for transmitter parameters PARAMS.MOD_SCH = USER_PARAMS.MOD_SCH; PARAMS.SPS = 4; % Sample per symbol % Create a root raised cosine pulse-shaping filter PARAMS.Nyquist_filter = rcosfir(.5 , 5, PARAMS.SPS, 1); % Bits per symbol, in this case bits per symbols is same as mod scheme PARAMS.BPS = USER_PARAMS.MOD_SCH; % Lookup tables for BPSK, QPSK, 8 - PSK and 16 - QAM using gray coding BPSK_Table = [(-1 + 0j) (1 + 0j)]; QPSK_Table = [(-.707 - .707j) (-.707 + .707j) (. 707 - .707j) (.707 + .707j)]; PSK8_Table = [(1 + 0j) (.7071 + .7071i) (-.7071 + .7071i) (0 + i)... (- 1 + 0i) (-.7071 - .7071i) (.7071 - .7071i) (0 - 1i)]; QAM_Table = [(- 3 + - 3j) (- 3 + - 1j) (- 3 + 3j) (- 3 + 1j) (- 1 + - 3j)... (- 1 + - 1j) (-1 + 3j) (- 1 + 1j) (3 + - 3j) (3 + - 1j)... (3 + 3j) (3 + 1j) (1 + - 3j) (1 + - 1j) (1 + 3j) (1 + 1j)]; % Constellation selection according to bits per symbol if(PARAMS.BPS == 1) PARAMS.const_Table = BPSK_Table; elseif(PARAMS.BPS == 2) PARAMS.const_Table = QPSK_Table; elseif(PARAMS.BPS == 3) PARAMS.const_Table = PSK8_Table; elseif(PARAMS.BPS == 4) PARAMS.const_Table = QAM_Table; else error(‘ERROR!!! This constellation size not supported’) end

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan

Chunk by chunk processing

13 function [out_data, STATES] = Modulator(in_data, PARAMS, STATES); % Bits to symbols conversion sym = reshape(in_data,PARAMS.BPS,length(in_data)/PARAMS.BPS)’; % Binary to decimal conversion sym_decimal = bi2de(sym); % Bit to symbol mapping const_sym = PARAMS.const_Table(sym_decimal+1); % Zero padding for up-sampling up_sym = upsample(const_sym,PARAMS.SPS); % Zero padded signal passed through Nyquist filter [out_data, STATES.filter_delayline] = filter(PARAMS.Nyquist_filter,1,up_sym, STATES.filter_delayline);

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan

Fixed-point v/s Floating-point Hardware

14

 Algorithms are developed in floating point format

using tools like Matlab

 Floating point processors and HW are expensive

 Fixed-point processors and HW are used in

embedded systems

 After algorithms are designed and tested then they

are converted into fixed-point implementation

 The algorithms are ported on Fixed-point processor

or application specific hardware

Representation of Numbers 16  In a digital design fixed or floating point numbers are represented in binary format  Types of Representation  one’s complement  sign magnitude  canonic sign digit (CSD)  two’s complement  In digital system design for fixed point implementation the canonic sign digit (CSD), and two’s complement are normally used

2’s Complement Arithmetic

17

Numbers

Signed Number Unsigned

Number

Positive

Number

Negative

Number

Example

19 1 0 1 1 (Negative number as MSB = 1) -8 + 2 + 1 = - 2 3 2 1 2 2 2 0

Equivalent Representation

20

Many design tools do not display numbers as 2’s complement signed numbers

A signed number is represented as an equivalent unsigned number

Equivalent unsigned value of an N-bit negative number is

2 N^ - |a|

Example

for -5 = 1011

N=

a=-

4

• |-5| = 16 – 5= +

In binary it is equivalent rep is 1011