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EE557-Index of terms
Computer architecture ISA Addressing mode Opcode Instruction format Frontside bus Northbridge Southbridge PCI bus Layered view of computer systems Role of the computer architect Interconnection Technology scaling Memory wall Disk access time Chip multiprocessor (CMP) Instruction-Level Parallelism (ILP) Thread-Level Parallelism (ILP) SAN, LAN,WAN networks Dynamic power Static (leakage) power Energy Name 4 ways to improve dynamic power Name 2 ways to improve static power Soft failure Hard failure Name a cause of intermittent failure Name two causes of transient faults CMOS endpoint Latency Response time Throughput Bandwidth Benchmarks Kernels SPEC TPC Arithmetic mean Harmonic mean Geometric mean CPI IPC Law of diminishing returns Why “optimize the common case”
Backward compatibility Accumulator architecture Stack architecture Operand alignment Big endian Displacement (register relative) addressing mode Immediate addressing mode Memory indirect addressing mode Register spilling Register filling Memory-to-memory ISA Load/store ISA Exceptions Traps Interrupts Precise exceptions Examples of precise exceptions Explain various exception types Microcode Microprogramming Micromachine Micro-PC RISC CISC Integer arithmetic Floating-point arithmetic Pipeline register Data hazards Difference between hazards and dependencies Control hazards Structural hazards Hazard detection Flushing Stalling Pipeline bubble RAW/WAW/WAR dependencies/hazards Operand forwarding Internal register forwarding Static instruction scheduling Latency of operation (operation latency) Repeat interval (initiation interval) Superpipelining N-way Superscalar Basic block Local scheduling Global scheduling
Trace cache Speculative instruction scheduling Instruction replay Wake-up bus Value prediction Renaming an instruction
VLIW Software pipelining Rotating registers cyclic scheduling Trace scheduling Predicated instructions Terminating exception Poison bits EPIC architecture Vector processor Vector register Vector stride Vector start-up time Vector length register Vector chaining Vector mask Scatter Gather Memory hierarchy Locality of reference Temporal locality Spatial locality Inclusion property Coherence in the memory hierarchy Cache mapping functions: Direct mapped, fully associative, set associative Cache indexing Cache replacement policies: LRU, FIFO, Pseudo-LRU, LIFO, Random Write-through Write-back Block offset Narrow cache Wide cache Content addressable memory Cold/compulsory misses Capacity misses Conflict misses Coherence misses Lockup-free cache
Non-blocking/lockup-free cache Primary/secondary misses MSHR sequential prefetching Hardware prefetch engines Software prefetching Princeton vs Harvard cache Virtual memory Protection Relocation Page fault Segment vs page Memory Synonyms Memory Homonyms Memory aliasing Superpages Swap-in/swap-out Effective address Virtual address Physical address Address translation Page table Hierarchical page table Page Table Base Register (PTBR) Translation Lookaside Buffer (TLB) Uncacheable memory MMU Table walking Page coloring Anti-aliasing hardware Superlinear speedup Multicomputer Components of a message: header/payload/checksum Crossbar Fully connected network Ring/mesh /torus/hypercube/tree Point-to-point interconnection Direct/indirect networks message/packet/payload/envelope Link/switch switch degree network diameter bisection bandwidth Flow control/switching/routing Routing in Butterfly/omega networks Dimension-order routing
Busy waiting Compare and Swap (CAS) Test and set (T&S) Swap Load-locked Store Conditional Fetch and Add (F&A) Test and Test and set Dual directory MSI-invalidate MSI-update MESI True/false sharing Fine/coarse grain sharing Performed (access) Globally performed Performed with respect to a processor Forwarding store buffer Temporal/coherence order Sequential consistency (conditions in an In order processor) Blocking load Memory Consistency Model (MCM) Relaxed memory model IBM 370 MCM (conditions in an In order processor) Total Store Order (TSO) (conditions in an In order processor) Relaxed Memory Order (RMO) Membar Weak Ordering (conditions in an In order processor) Release consistency (conditions in an in order processor) Core multithreading Block multithreading Interleaved multithreading Simultaneous multithreading
