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Page 1 of 6 C5 570 HOUR TEST #1 March 12, 2003 Name (Last, First): key SSN (4 digits): ROW: COL: IMPORTANT: PLEASE WRITE NEATLY AND LEGIBLY. ILLEGIBLE ANSWERS WILL NOT BE GRADED. This is a elosed-book exam. Only a half letter-size page cheat-sheet is allowed. (The cheat sheet must be one-of-a- kind, hand written by the student who is taking the exam and must be signed and turned in along with the exam paper. Write your answers in space provided, immediately below the question. 1. Given is en excerpt from user and kernel images. Suppose all addresses are in HEX, as well as any other argument preceded with "$". Also suppose that all instructions take exactly two bytes. Exception Vector Virtual Table nen Kemet code address User code index 0} 0000 1F00 0000 20EE | RTE Q00B 7AD0[....------ 4| 0000 1AA8 0000 20F0 | MOVE SOFDD 000B 7A02| MOVE #13,71 2 |_0000 1AB4 0000 20F2| OR ri,SR : oo0B 7A04[ PUSH 11 3 | 0000 1EEO 30000 20F4 | RTE 0008 7A06 | TRAP #4 A |_ 0000 20F0 ooo020F6;---------- 0008 7408 | MOVE 11,12 5[ 0000 1BBC OOOB 7ADA] veer: 6| 0000 2F00 xx 7 | 0000 1FOE Tl } Processor Status Register (SR) 16 13 wo 8 BT 0 T $ lel alt If bits 10-8 are all 0, interrupts are enabled '2| Ti] 9} if bits 10-6 are ali 1, interrupts are disabled ag Torte F (a) [10.POINTS] Fill-in the values of the program counter (PC) and processor status register (SR) in table below, which correspond to various check points. Check point PC ° SR Immediately before fetching TRAP instruction oooB 7aoe ¢ & 00xx ("'xx" means.don't care) 2 (before fetching nextinseustion) ‘oo00 20FO|* toxx Immediately before RTE instruction 20000 AYFAR OFXX Immediately after RTE instruction 10009 F A O& {eox x (b) [12 POINTS] Modify the trap handler so that the interrupts stay disabled after return from trap. (you may use instructions: PUSH x1 and POP r1 for kernel stack manipulation, in addition to MOVE and OR instructions (see above). pe vr, pep. Mh : OT OY 1 Hd Ke xx ORT A$ 0700)" push ¥; push r4 MoV FHo7at On if, . 
