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ECE 746 Project Specification: Testing True Random Number Generators, Study Guides, Projects, Research of Electrical and Electronics Engineering

George Mason University (GMU)Electrical and Electronics Engineering

A project proposal for testing the randomness and suitability of true random number generators (trngs) in the context of commercial-grade cryptographic systems. The project involves obtaining sets of random values from a new fpga-based trng design and testing them using the nist statistical test suite for random and pseudorandom number generators. The document also discusses the project setup, including the required software and testing procedure.

Typology: Study Guides, Projects, Research

Pre 2010

Uploaded on 02/10/2009

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ECE 746 – Paul Kohlbrenner – 2/16/2002 – Project Specification Page 1 of 2
Paul Kohlbrenner, ECE746, Spring 2002
Project Specification, due 2/16/2002
Semester Project:
Testing True Random Number Generators
Introduction:
Many cryptographic processes require a source of random values. In some systems these values are
supplied by Pseudo Random Number Generators (PRNGs). While PRNGs are suitable for many
situations, for secure cryptographic use a True Random Number Generator (TRNG) is needed.
TRNGs are generally implemented by sampling some unpredictable physical phenomena such as
radioactive decay or thermal noise. The sampled values (with any bias removed) are then stored for
later use by the consuming cryptographic process.
In this ECE746 project I propose that I work to obtain sets of random values from one or more
physical sources. I will test the values to judge their “randomness” and suitability for use in
commercial grade cryptographic systems. The primary physical source of random values will be a
new design for a TRNG implemented in an FPGA.
I expect to use the NIST “Statistical Test Suite For Random And Pseudorandom Number Generators
For Cryptographic Applications” to provide a test bed for this project.
Specification for a Software Project:
1. Language:
The NIST suite is written in C. Any code that I need to write will also be written in C. I would like
to have everything compile and run with the Microsoft Visual C++ compiler (version 6) since that’s
the most available platform for me. Unfortunately, the NIST suite is configured for a Solaris box
running on a SPARC processor. I have access to several of these kinds of machines at work (and
presumably at GMU) so if I can’t get the system to run on a PC I will switch to one of these
machines.
2. Additional Software:
As mentioned above, I will be using the NIST suite. I will be using board specific drivers to access
the FPGA test board.
3. Detailed Specification:
I don’t yet know the exact setup for the FPGA board so it is difficult to specify what the input will
look like. The NIST suite accepts files of any length in either ASCII format (“1” and “0” characters)
or in binary format. The output of the suite is two log files with the results of running the sixteen
tests in the suite.
4. Brief description of the function:
pf2

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ECE 746 – Paul Kohlbrenner – 2/16/2002 – Project Specification Page 1 of 2

Paul Kohlbrenner, ECE746, Spring 2002 Project Specification, due 2/16/

Semester Project:

Testing True Random Number Generators

Introduction:

Many cryptographic processes require a source of random values. In some systems these values are supplied by Pseudo Random Number Generators (PRNGs). While PRNGs are suitable for many situations, for secure cryptographic use a True Random Number Generator (TRNG) is needed.

TRNGs are generally implemented by sampling some unpredictable physical phenomena such as radioactive decay or thermal noise. The sampled values (with any bias removed) are then stored for later use by the consuming cryptographic process.

In this ECE746 project I propose that I work to obtain sets of random values from one or more physical sources. I will test the values to judge their “randomness” and suitability for use in commercial grade cryptographic systems. The primary physical source of random values will be a new design for a TRNG implemented in an FPGA.

I expect to use the NIST “Statistical Test Suite For Random And Pseudorandom Number Generators For Cryptographic Applications” to provide a test bed for this project.

Specification for a Software Project:

  1. Language:

The NIST suite is written in C. Any code that I need to write will also be written in C. I would like to have everything compile and run with the Microsoft Visual C++ compiler (version 6) since that’s the most available platform for me. Unfortunately, the NIST suite is configured for a Solaris box running on a SPARC processor. I have access to several of these kinds of machines at work (and presumably at GMU) so if I can’t get the system to run on a PC I will switch to one of these machines.

  1. Additional Software:

As mentioned above, I will be using the NIST suite. I will be using board specific drivers to access the FPGA test board.

  1. Detailed Specification:

I don’t yet know the exact setup for the FPGA board so it is difficult to specify what the input will look like. The NIST suite accepts files of any length in either ASCII format (“1” and “0” characters) or in binary format. The output of the suite is two log files with the results of running the sixteen tests in the suite.

  1. Brief description of the function:

ECE 746 – Paul Kohlbrenner – 2/16/2002 – Project Specification Page 2 of 2

It will probably be possible to plug the output of the TRNG directly into the test suite allowing real time analysis of the TRNG.

  1. Procedure for testing:

The NIST suite will be tested with its supplied test vectors and with other “random” sets of data. I will evaluate the PRNG I wrote for my ECE646 project last semester. I will also attempt to obtain sets of random values from a source on the Internet.

I will also “eyeball” the output of the FPGA device as a sanity check before running it through the NIST suite.

  1. Plan of Experiments:

I will make a number of runs of the FPGA device gathering data into large files. I will analyze each set of data with the NIST suite. If possible I will hook the device directly to the NIST suite and make several overnight runs.

  1. Time Schedule:

I have already begun trying to port the NIST suite to a PC running Windows. I hope to complete this activity (both the port and initial testing of the port) by March 2nd^. I will spend March making test runs with the FPGA device and analyzing results with the NIST suite. I will spend April interpreting the results of the NIST suite and writing the final report.

  1. Possible changes:

If everything goes really well and I’m ahead of schedule in March I would like to try to sample other sources of physical random values. I have a specification for a modified geiger counter that can generate random values.

  1. Other:

I am taking Dr. Mark’s High Speed Networks course this semester (ECE742). My project in that class is to simulate a multi-stage switch and analyze the blocking probability. I will need a source of random values to drive the simulation. I plan to use some of the random values obtained in the project.