The ARM Instruction Set, Study notes of Architecture

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The ARM Instruction Set

ARM

Advanced RISC Machines

Processor Modes

• The ARM has six operating modes:

• User (unprivileged mode under which most tasks run)
• FIQ (entered when a high priority (fast) interrupt is raised)
• IRQ (entered when a low priority (normal) interrupt is raised)
• Supervisor (entered on reset and when a Software Interrupt instruction is executed)
• Abort (used to handle memory access violations)
• Undef (used to handle undefined instructions)

• ARM Architecture Version 4 adds a seventh mode:

• System (privileged mode using the same registers as user mode)

Register Organisation

General registers and Program Counter Program Status Registers r15 (pc)

r

r r r r r r r

r

r

r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) cpsr cpsr cpsr cpsr cpsr r14_fiq^ r13_fiq r12_fiq r10_fiq r11_fiq^ r9_fiq r8_fiq

• User32 / System FIQ32 Supervisor32 Abort32 IRQ32 Undefined r14 (lr)r13 (sp) r14_svcr13_svc r14_abtr13_abt r14_irqr13_irq r14_undefr13_undef
  • r cpsr sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqspsr_fiq spsr_svc spsr_abt sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqspsr_irq
  • r10 r11 r
    • r
    • r
    • r4 r
    • r2 r
    • r
    • r
    • r6 r
      • r4 r
      • r2 r
      • r
      • r
      • r
        • r
        • r10 r11 r
          • r
          • r
          • r4 r
          • r2 r
          • r
          • r
          • r
            • r
            • r10 r11 r
              • r
              • r
              • r4 r
              • r2 r
              • r
              • r
              • r
                • r
                • r10 r11 r
                  • r - r - r4 r - r2 r - r - r - r - r - r10 r11 r - r - r - r4 r - r2 r - r - r - r

Register Example:

User to FIQ Mode

spsr_fiq^ cpsr

r

r

r

r

r

r4 r

r2^ r

r r r

r15 (pc)

r14_fiq^ r13_fiq

r12_fiq

r10_fiq r11_fiq

r9_fiqr8_fiq

r14 (lr)r13 (sp)

r

r10 r11^ r

r

User mode CPSR copied to FIQ mode SPSR

cpsr

r15 (pc)^ r14 (lr)

r13 (sp)^ r

r10 r11^ r

r

r

r4 r

r2^ r

r r r

r14_fiq^ r13_fiq

r12_fiq

r10_fiq r11_fiq^ r9_fiq

r8_fiq

Return address calculated from User modePC value and stored in FIQ mode LR

Registers in use (^) Registers in use

EXCEPTION

User Mode FIQ Mode

spsr_fiq

The Program Status Registers

(CPSR and SPSRs)

Copies of the ALU status flags (latched if the instruction has the "S" bit set).

N = N egative result from ALU flag. Z = Z ero result from ALU flag. C = ALU operation C arried out V = ALU operation o V erflowed

*** Interrupt Disable bits. I** = 1, disables the IRQ. F = 1, disables the FIQ. *** T Bit (Architecture v4T only)** T = 0, Processor in ARM state T = 1, Processor in Thumb state

*** Condition Code Flags**

N Z C V Mode

31 28 8 4 0 I F T

*** Mode Bits M** [4:0] define the processor mode.

Logical Instruction Arithmetic Instruction

Flag

Negative No meaning Bit 31 of the result has been set (N=‘1’) Indicates a negative number in signed operations

Zero Result is all zeroes Result of operation was zero (Z=‘1’)

Carry After Shift operation Result was greater than 32 bits (C=‘1’) ‘1’ was left in carry flag

oVerflow No meaning Result was greater than 31 bits (V=‘1’) Indicates a possible corruption of the sign bit in signed numbers

Condition Flags

• When an exception occurs, the core:

• Copies CPSR into SPSR_
• Sets appropriate CPSR bits
  If core implements ARM Architecture 4T and is currently in Thumb state, then  ARM state is entered.
  Mode field bits
  Interrupt disable flags if appropriate.
• Maps in appropriate banked registers
• Stores the “ return address ” in LR_
• Sets PC to vector address

• To return, exception handler needs to:

• Restore CPSR from SPSR_
• Restore PC from LR_

Exception Handling

and the Vector Table

0x

0x0000001C

0x

0x

0x

0x0000000C

0x

0x

Reset Undefined Instruction

FIQ

IRQ

Reserved

Data Abort

Prefetch Abort

Software Interrupt

The Instruction Pipeline

• The ARM uses a pipeline in order to increase the speed of the flow of instructions to the processor.

• Allows several operations to be undertaken simultaneously, rather than serially.

• Rather than pointing to the instruction being executed, the PC points to the instruction being fetched.

FETCH

DECODE

EXECUTE

Instruction fetched from memory

Decoding of registers used in instruction

Register(s) read from Register Bank Shift and ALU operation Write register(s) back to Register Bank

PC

PC - 4

PC - 8

ARM

ARM Instruction Set Format

Instruction type Data processing / PSR Transfer Multiply Long Multiply (v3M / v4 only) Swap Load/Store Byte/Word Load/Store Multiple Halfword transfer : Immediate offset (v4 only) Halfword transfer: Register offset (v4 only) Branch Branch Exchange (v4T only) Coprocessor data transfer Coprocessor data operation Coprocessor register transfer Software interrupt

Cond 0 0 I Opcode S Rn Rd Operand Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm

Cond 0 0 0 1 0 B 0 0 Rn Rd 0 0 0 0 1 0 0 1 Rm Cond 0 1 I P U B W L Rn Rd Offset Cond 1 0 0 P U S W L Rn Register List

Cond 0 0 0 0 1 U A S RdHi RdLo Rs 1 0 0 1 Rm

Cond 0 0 0 P U 1 W L Rn Rd Offset1 1 S H 1 Offset

Cond 1 0 1 L Offset

Cond 1 1 0 P U N W L Rn CRd CPNum Offset Cond 1 1 1 0 Op1 CRn CRd CPNum Op2 0 CRm Cond 1 1 1 0 Op1 L CRn Rd CPNum Op2 1 CRm Cond 1 1 1 1 SWI Number

Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rn

Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1 Rm

31 2827 1615 87 0

Conditional Execution

• Most instruction sets only allow branches to be executed conditionally.
• However by reusing the condition evaluation hardware, ARM effectively increases number of instructions.

• All instructions contain a condition field which determines whether the CPU will execute them.
• Non-executed instructions soak up 1 cycle.
  • Still have to complete cycle so as to allow fetching and decoding of following instructions.

• This removes the need for many branches, which stall the pipeline ( cycles to refill).

• Allows very dense in-line code, without branches.
• The Time penalty of not executing several conditional instructions is frequently less than overhead of the branch or subroutine call that would otherwise be needed.

Using and updating the

Condition Field

• To execute an instruction conditionally, simply postfix it with the appropriate condition:

• For example an add instruction takes the form:
  • ADD r0,r1,r2 ; r0 = r1 + r2 (ADDAL)
• To execute this only if the zero flag is set:
  • ADDEQ r0,r1,r2 ; If zero flag set then… ; ... r0 = r1 + r

• By default, data processing operations do not affect the condition flags (apart from the comparisons where this is the only effect). To cause the condition flags to be updated, the S bit of the instruction needs to be set by postfixing the instruction (and any condition code) with an “S”.

• For example to add two numbers and set the condition flags:
• ADDS r0,r1,r2 ; r0 = r1 + r ; ... and set flags

• Branch : B{} label

• Branch with Link : BL{} sub_routine_label

• The offset for branch instructions is calculated by the assembler:

• By taking the difference between the branch instruction and the target address minus 8 (to allow for the pipeline).
• This gives a 26 bit offset which is right shifted 2 bits (as the bottom two bits are always zero as instructions are word – aligned) and stored into the instruction encoding.
• This gives a range of
  32 Mbytes.

Branch instructions (1)

31 28 24 0 Cond 1 0 1 L Offset

Condition field

Link bit 0 = Branch 1 = Branch with link

27 25 23

Data processing Instructions

• Largest family of ARM instructions, all sharing the same instruction format.
• Contains:

• Arithmetic operations
• Comparisons (no results - just set condition codes)
• Logical operations
• Data movement between registers

• Remember, this is a load / store architecture

• These instruction only work on registers, NOT memory.

• They each perform a specific operation on one or two operands.

• First operand always a register - Rn
• Second operand sent to the ALU via barrel shifter.

• We will examine the barrel shifter shortly.

Arithmetic Operations

• Operations are:

• ADD operand1 + operand
• ADC operand1 + operand2 + carry
• SUB operand1 - operand
• SBC operand1 - operand2 + carry -
• RSB operand2 - operand
• RSC operand2 - operand1 + carry - 1

• Syntax:

• {}{S} Rd, Rn, Operand

• Examples

• ADD r0, r1, r
• SUBGT r3, r3, #
• RSBLES r4, r5, #