The Von Neumann Model, Exercises of Architecture

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The Von Neumann Model

The Stored Program Computer

1943: ENIAC Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939?) Hard-wired program -- settings of dials and switches. 1944: Beginnings of EDVAC among other improvements, includes program stored in memory 1945: John von Neumann wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC The basic structure proposed in the draft became known as the “von Neumann machine” (or model). a memory , containing instructions and data a processing unit , for performing arithmetic and logical operations a control unit , for interpreting instructions For more history, see http://www.maxmon.com/history.htm

Memory

k x m array of stored bits Address unique ( k -bit) identifier of location Contents m -bit value stored in location Basic Operations: LOAD read a value from a memory location STORE write a value to a memory location

**-

0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 10100010**

Interface to Memory

How does processing unit get data to/from memory? MAR: Memory Address Register MDR: Memory Data Register To LOAD a location (A):

1. Write the address (A) into the MAR.
2. Send a “read” signal to the memory.
3. Read the data from MDR.
4. To STORE a value (X) to a location (A):
5. Write the data (X) to the MDR.
6. Write the address (A) into the MAR.
7. Send a “write” signal to the memory.

MEMORY

MAR MDR

Input and Output

Devices for getting data into and out of computer memory Each device has its own interface, usually a set of registers like the memory’s MAR and MDR LC-3 supports keyboard (input) and monitor (output) keyboard: data register (KBDR) and status register (KBSR) monitor: data register (DDR) and status register (DSR) Some devices provide both input and output disk, network Program that controls access to a device is usually called a driver. INPUT Keyboard Mouse Scanner Disk OUTPUT Monitor Printer LED Disk

Control Unit

Orchestrates execution of the program Instruction Register (IR) contains the current instruction. Program Counter (PC) contains the address of the next instruction to be executed. Control unit: reads an instruction from memory the instruction’s address is in the PC interprets the instruction, generating signals that tell the other components what to do an instruction may take many machine cycles to complete CONTROL UNIT PC IR

Instruction

The instruction is the fundamental unit of work. Specifies two things: opcode : operation to be performed operands : data/locations to be used for operation An instruction is encoded as a sequence of bits. (Just like data!) Often, but not always, instructions have a fixed length, such as 16 or 32 bits. Control unit interprets instruction: generates sequence of control signals to carry out operation. Operation is either executed completely, or not at all. A computer’s instructions and their formats is known as its Instruction Set Architecture (ISA).

Example: LC-3 ADD Instruction

LC-3 has 16-bit instructions. Each instruction has a four-bit opcode, bits [15:12]. LC-3 has eight registers (R0-R7) for temporary storage. Sources and destination of ADD are registers. “Add the contents of R2 to the contents of R6, and store the result in R6.”

Instruction Processing: FETCH

Load next instruction (at address stored in PC) from memory into Instruction Register (IR). Copy contents of PC into MAR. Send “read” signal to memory. Copy contents of MDR into IR. Then increment PC, so that it points to the next instruction in sequence. PC becomes PC+1.

EA

OP

EX

S

F

D

Instruction Processing: DECODE First identify the opcode. In LC-3, this is always the first four bits of instruction. A 4-to-16 decoder asserts a control line corresponding to the desired opcode. Depending on opcode, identify other operands from the remaining bits. Example: for LDR, last six bits is offset for ADD, last three bits is source operand #

EA

OP

EX

S

F

D

Instruction Processing: FETCH OPERANDS Obtain source operands needed to perform operation. Examples: load data from memory (LDR) read data from register file (ADD)

EA

OP

EX

S

F

D

Instruction Processing: EXECUTE Perform the operation, using the source operands. Examples: send operands to ALU and assert ADD signal do nothing (e.g., for loads and stores)

EA

OP

EX

S

F

D

Changing the Sequence of Instructions In the FETCH phase, we increment the Program Counter by 1. What if we don’t want to always execute the instruction that follows this one? examples: loop, if-then, function call Need special instructions that change the contents of the PC. These are called control instructions. jumps are unconditional -- they always change the PC branches are conditional -- they change the PC only if some condition is true (e.g., the result of an ADD is zero)

Example: LC-3 JMP Instruction

Set the PC to the value contained in a

register. This becomes the address of the

next instruction to fetch.

“Load the contents of R3 into the PC.”