To Boldly Do What Can't be Done - Asynchronous Design for All | ECE 3991, Exams of Electrical and Electronics Engineering

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To Boldly Do What Can’t Be Done:

Asynchronous Design for All

Kenneth S. Stevens University of Utah

Scaling

l Moore’s Law

u transistor counts double every one to two years u Cost has followed inverse trend

l Imagine this in other scenarios...

l Will scaling continue?

Education and Engineering

Observation: Our Engineering proofs and professors

appeared to be wrong...

Why?

1. What affect do our assumptions have on our results?

2. Disruptive ideas change the foundations of our work.

“Learn the rules so you know how to break them

properly.”

Dalai Lama

Dynamic Gate Example

Advantages: low latency, high gain

Disadvantages: high power, noise

Why are dynamic gates high power?

l They are high gain devices - is this contradictory?

Assumption: We connect precharge to the clock.

⇒ Low data activity, high precharge activity due to clocked

configuration create power problem.

Rule Breaker: Using dynamic gates as set-reset gates in

sequential asynchronous logic results in over 2 × the performance

and energy efficiency of static gates.

Noise in Dynamic Gates

Assumption: We use a simple jam-latch for a keeper to reduce noise in dynamic gates.

unfooted, f = ab

b

a

p e s s s o

e se

unfooted, f = ab

b

a

p e s s s o

e

s a e^ b e

p

s e

Is the Complementary Dynamic Gate keeper better?

VLSI is becoming Ubiquitous

Proposition: The price of a product is proportional to it’s weight

Technology and Art

Technology is: formal predictable creative artistic

How do we combine disparate requirements?

Asynchronous Design:

What are the Right Questions?

What are your questions?

What are the Right Questions?

l What is async design?

l Why does async have a bad reputation?

l Are reactive designs a good thing?

l Is asynchronous design really faster?

l Where do theoretical advantages come from?

l What is relationship of Async and PVT variations?

l What are the overheads for handshaking?

l Is asynchronous design lower power?

l How does one achieve an advantage with this stuff?

l Are async designs { reliable, predictable, repeatable }?

What are the Right Questions?

l What are typical protocols?

l Various protocol benefits and disadvantages?

l What is the relationship between timing and async ckts/protocols?

l Are races versus speed paths a big issue?

l What is key requirement for async/protocol design?

l There are a million methodologies - which do I choose?

What are the Right Questions?

l What classes of circuits should I use?

l Do I need custom cell libraries?

l Why would one want to adopt async? (The Big 3)

l Why would one not want to do async?

l Should I do async?

Traditional Clocked Design

l Characteristics u Precise synchronization to central clock u Low skew clock distribution network u Provides same frequency and phase everywhere l Faces challenges to reuse u Optimality of frequency, re-pipelining for frequency changes, etc. u Wires scale differently than gates: up to 40% dead cycle time needed to account for wire scaling for future process shrinks to avoid redesign

l Desire to move toward decentralized clocking u Data valid bit emulates locality of self-timing u clock gating, multiple frequencies, reuse

Traditional Async Design

l Characteristics u statistical behavior based on function & data u State transitions when data becomes valid u Modular interfaces using handshake protocols

l Faces challenges with deployment u Synchronization, validation challenging with clocked systems u Hazard-free logic: control and data u Delay-Insensitive protocols inefficient

l Moving toward increased timing in design u Building data with timing reference u Relative timing in protocols