Docsity
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Docsity AI
Docsity AI
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search for your university

Find the specific documents for your university's exams

Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

Tomasulo’s Algorithm - Intro to Computer Architecture - Homework, Exercises of Computer Architecture and Organization

In the course of intro to computer architecture, the main points are:Tomasulo’s Algorithm, Load Buffer, Instruction Unit, Register Value, Common Data Bus, Register Specifiers, Reservation Station, Functional Unit, Example of Dynamic Scheduling, Read Operands, Memory References, Dynamic Disambiguation

Typology: Exercises

2012/2013

Uploaded on 05/06/2013

anurati
anurati 🇮🇳

4.2

(24)

121 documents

1 / 2

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Example using Tomasulo’s Algorithm
6
5
4
3
2
1
Load Buffer
From Memory From Instruction Unit
Busy Tag Data
F0
F2
F4
F6
F8
F10
FP op.s queue
FP Registers
FP Adders
8
9
10
11
12
13
FP Multiplers
Store Buffer
To All
Tags
Tag Data Tag Data Tag Data Tag Data
Common Data Bus
To Memory
Tag Data
LD F6, 34 (R2)
LD F2, 45 (R3)
MULTD F0,F2,F4
SUBD F8, F6, F2
DIVD F10,F0,F6
ADDD F6, F8, F2
(front)
(rear)
Reservation
Stations
As instructions are issued, register specifiers for pending operands are
renamed to names of reservation stations.
When both operands are available and a functional unit is available, the
instruction in the reservation station can be executed.
When the result is available, it is put on the CDB with the reservation that
produced it. All reservation stations waiting to use that result will update
their operands simultaneously.
Operation:
Busy - indicates if current value in reg.
0 - available in reg. 1 - not avail.
Tag - reservation that will supply
register value.
7
Lecture 7 Page 1
Docsity.com
pf2

Partial preview of the text

Download Tomasulo’s Algorithm - Intro to Computer Architecture - Homework and more Exercises Computer Architecture and Organization in PDF only on Docsity!

Example using Tomasulo’s Algorithm

6 5 4 3 2 1

Load Buffer

From Memory From Instruction Unit

Busy Tag^ Data F F F F F F

FP op.s queue

FP Registers

FP Adders

FP Multiplers

Store Buffer

To All Tags

Tag Data Tag Data Tag Data Tag Data

Common Data Bus

To Memory

Tag Data

LD F6, 34 (R2)

LD F2, 45 (R3)

MULTD F0,F2,F

SUBD F8, F6, F

DIVD F10,F0,F

ADDD F6, F8, F

(front)

(rear)

Reservation Stations

As instructions are issued, register specifiers for pending operands are renamed to names of reservation stations.

When both operands are available and a functional unit is available, the instruction in the reservation station can be executed.

When the result is available, it is put on the CDB with the reservation that produced it. All reservation stations waiting to use that result will update their operands simultaneously.

Operation:

Busy - indicates if current value in reg. 0 - available in reg. 1 - not avail. Tag - reservation that will supply register value.

7

Lecture 7 Page 1

Docsity.com

Download and Read Appendix I of the Textbook from Stallings web-site:

Tomasulo's Algorithm is an example of dynamic scheduling. In dynamic scheduling the stages of the

pipeline are split into three stages to allow for out-of-order execution:

1. Issue - decodes instructions and checks for structural hazards. Instructions are issued in-order through a

FIFO queue to maintain correct data flow. If there is not a free reservation station of the appropriate type,

the instruction queue stalls.

2. Read operands - waits until no data hazards, then read operands

3. Write result - send the result to the CDB to be grabbed by any waiting register or reservation stations

All instructions pass through the issue stage in order, but instructions stalling on operands can be bypassed

by later instructions whose operands are available.

RAW hazards are handled by delaying instructions in reservation stations until all their operands are

available.

WAR and WAW hazards are handled by renaming registers in instructions by reservation station numbers.

Load and Store instructions to different memory addresses can be done in any order, but the relative order of

a Store and accesses to the same memory location must be maintained. One way to perform dynamic

disambiguation of memory references, is to perform effective address calculations of Loads and Stores in

program order in the issue stage.

 Before issuing a Load from the instruction queue, make sure that its effective address does not match the

address of any Store instruction in the Store buffers. If there is a match, stall the instruction queue until,

the corresponding Store completes. (Alternatively, the Store could forward the value to the

corresponding Load )

 Before issuing a Store from the instruction queue, make sure that its effective address does not match the

address of any Store or Load instructions in the Store or Load buffers.

1. If ADD and SUB take one cycle and MUL takes 7 cycles to execute, then what would be the first

instruction to complete using Tomasula's algorithm on the following program?

MUL R6, R4, R

ADD R2, R6, R

STORE R2, 8(R6)

ADD R2, R3, R

SUB R4, R5, R

LOAD R4, 16(R4)

ADD R1, R2, R

b) How does register renaming help the STORE instruction save the correct R2 value to memory while still

allowing later instructions to execute?

Lecture 7 Page 2

Docsity.com