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Learning Outcomes
This chapter deals with a variety of circuits involving semiconductor devices. These will
include bias and stabilisation for transistors, and small-signal a.c. amplifier circuits using both
BJTs and FETs. The use of both of these devices as an electronic switch is also considered.
On completion of this chapter you should be able to:
1 Understand the need for correct biasing for a transistor, and perform calculations to obtain
suitable circuit components to achieve this effect.
2 Understand the operation of small-signal amplifiers and carry out calculations to select
suitable circuit components, and to predict the amplifier gain figure(s).
3 Understand how a transistor may be used as an electronic switch, and carry out simple
calculations for this type of circuit.
35
1 Transistor Bias
In order to use a transistor as an amplifying element it needs to
be biased correctly. Although d.c. signals may be amplified, the
amplification of a.c. signals is more common. However, the bias is
provided by d.c. conditions. Consider a common emitter connected
BJT and its input characteristic as illustrated in Fig. 1. The inclusion
of resistor RC is not required at this stage, but would be present in any
practical amplifier circuit, so is shown merely for completeness. This
resistor is called the collector load resistor.
With the switch in position ‘ 1 ’ the value of forward bias V BEQ has been
chosen such that it coincides with the centre of the linear portion of the
input characteristic. This point on the characteristic is identified by the
letter Q, because, without any a.c. input signal connected, the transistor
is said to be in its quiescent state. Under this condition the base current
will be I BQ with the corresponding values of collector and emitter
currents being I CQ and I EQ respectively. The use of capital letters in
the subscripts indicates d.c. quantities, and the letter Q that they are
quiescent values.
Consider now what happens when the switch is moved to position ‘ 2 ’ ,
thus connecting the a.c. signal generator between base and emitter.
The a.c. signal Vbe (note the use of lower case letters to indicate an
a.c. quantity) from the generator would normally vary about 0V, but
it will now be superimposed on the quiescent d.c. bias level VBEQ.
Thus the effective bias voltage will vary in sympathy with the input
signal, causing a corresponding variation of the base current about its
quiescent d.c. level as shown. Due to transistor action there will be
corresponding variations of both collector and emitter currents about
their quiescent values.
Figure 2 shows the effect when a different d.c. bias voltage, and hence
different Q point, is selected.
B
BQ
O VBE
V (^) BEQ
δVbe
δb Q EQ
VCC
VCEQ
RC
CQ
BQ VBEQ
‘2’ ‘1’
Vbe
Fig. 1
B
O VBE
VBEQ
δVbe
δb
Q
Fig. 2
This approximation is valid since when selecting a value for RB the
nearest preferred value would have to be used. This is demonstrated in
the following example.
Worked Example 1
Q A simply biased transistor circuit is shown in Fig. 4. The required quiescent values for base current
and base-emitter voltage are 60 μ A and 0.8V respectively. Determine a suitable value for resistor RB.
A
VCC 9 V; I BQ 60 10 ^6 A; VBEQ 0.8 V
Using equation (2) we have
R V^ V
R
B CC^ BEQ BQ B
^
( ) ohm ( )
k
I
6
1 Ans Using the approximation of equation (2) gives
R V
R
B CC BQ B
I
ohm
k
1 Ans Now, the nearest preferred value would be 1 50 k , so the use of equation (2) is justified. Although this bias circuit has the advantage of simplicity, it cannot overcome the problem of the bias and hence Q point varying with temperature change, and the even more serious problem of thermal runaway.
3 Thermal Runaway
When the transistor is operating in a circuit, the collector current will
tend to cause a temperature increase, with a consequent increase of
RB
80 μA
BQ
VCC 9 V
V (^) BEQ
RC
0.8 V
Fig. 4
transistor current gain hFB. For example, assume that hFB increases
from 0.98 to 0.99 under this condition. This is an increase of only
about 1%, and so will result in only a very small increase of collector
current. For this reason, if the transistor is connected in the common
base configuration it will be relatively stable, and the simple bias
circuit described will usually be acceptable.
Consider now the effect of the same increase of temperature when this
same transistor is connected in the common emitter configuration. h FB
will increase from 0.98 to 0.99 as before, but the effect on hFE is more
dramatic as shown below.
When ;
When
h h
h
h
h h
FB FE
FB FB
FB FE
. ; .9^99
Thus for the same temperature rise the transistor current gain has more
than doubled, with a corresponding increase in collector current. This
will result in a further increase in temperature, a further small increase
in hFB , and a further massive increase in hFE , etc.
The process is a cumulative one known as thermal runaway which
will result in the rapid destruction of the transistor. Since the runaway
condition is the result of a rapid increase of collector current, then
some means of preventing this needs to be employed.
4 Bias with Thermal Stabilisation
One simple method of providing a degree of thermal stability is to
connect the bias resistor directly to the collector, as shown in Fig. 5.
RB
B
C (^) VCC
VBE E
VB
VCE
RC
Fig. 5
As a result of temperature rise, I C will tend to rise. This will be
mirrored by a corresponding increase in emitter current IE. However,
the base potential V 2 is fi xed, so the overall bias VBE will tend to
decrease, which in turn will tend to reduce IC. Once more the system
has gone full circle such that the original tendency for collector current
to increase has been counteracted. This effect is illustrated below,
where the arrows show the tendencies for the various quantities to
increase or decrease.
I C I E V E V VE I B IC
(bias)
When calculating suitable values for the bias components the following
points should be borne in mind.
(a) For good thermal stability the p.d. across RE should be about
VCC /10 volt.
(b) The value of R 2 should be at least 10 R E ohm.
(c) The current I 1 through R 1 should be approximately 10 to 20 I BQ.
(d) The collector-emitter voltage V CE should be approximately
VCC /2 volt.
These points are best illustrated by means of the following example.
Worked Example 2
Q For the circuit of Fig. 6 the transistor has a current gain, hFE 80 and the collector supply
voltage, VCC 1 0V. The required bias conditions are VBE 0.7V, and I C 1 mA. Determine suitable values for resistors R 1 , R 2 , RE and RC.
A
V (^) CC 1 0 V; I C 10 ^3 A; VBE 0.7 V; hFE 80 Since , then mA and if / , then V
he
I E I C I E
VE VCC VE
nnce, ohm
k
R V
R
E E E E
I
Ans if , then k ( ) volt so,
R R
R
V V V
V V V
E
BE E BE E
2 2 2 2
1 Ans
2 2 2 4 2
V
amp
and, mA
I
I
V
R
I I
I
I I I
B C FE B B
h
3
2
μA or mA .. 1 825 mA
V V V
R V
R
1 CC 1 1 1 1
2
3
volt V
ohm
I.
k , and the nearest preferred value is 47 k (
Ans VC VCC VEE CE CE CC C
C C C
V V V
V
R V
) volt ( ) assuming that / V
I
oohm
k , and the nearest preferred value is 3.
RC kk Ans
6 Biasing Circuits for FETs
In general, FETs are much simpler devices than BJTs, and since the gate
draws negligible current the bias arrangements can also be simpler. FETs
also have the advantage that they tend not to suffer thermal runaway,
though change in temperature can cause drift of the Q point.
The simplest arrangement for a common source circuit is shown in
Fig. 7. The resistor R D is equivalent to the collector resistor R C in the
BJT circuit.
VGS RG
VDS D
D
RD
RS VS
VDD
Fig. 7
Essentially, the gate-source bias voltage is provided by R S. Resistor RG
will be a high value resistor, typically in megohms, which is used to
connect the 0V rail to the gate. Now, you may well ask the question,
how can a large value resistor act as a direct connection between the
0V rail and the gate? The answer is very simple. Since the gate draws
negligible current there will be negligible current through RG , hence
negligible voltage drop across it, so both ends of the resistor must be
at the same potential, i.e. 0V. The FET itself has a very high input
impedance, and therefore will have almost no loading effect on a signal
block any d.c. level (normally 0V) from the signal generator affecting
the d.c. bias conditions of the transistor. Similarly, C 2 couples the
a.c. signal developed across RC to the output terminals, but prevents
the quiescent collector voltage from affecting the output waveform.
The values of these capacitors are chosen so that they will have very
low reactance at the signal frequency, and therefore are virtually
‘ transparent ’ to the a.c. signal, i.e. they will have imposed negligible
voltage drop. The effect of the capacitors on the various currents and
voltages is illustrated in Fig. 10.
RB RC C C 1
ib
vi vi vbe
vo vce
C i (^) C
B ib
E ie
B
VCC
VBE
V (^) CE vCE
Fig. 9
Fig. 10
0
vi
(a) input signal
0
VBE
vbe
(b) base–emitter voltage
0
B
ib
(c) base current
C
iC
0 (d) collector current
0
vo
(f) output voltage
VCE
vCE^
0 (e) collector–emitter voltage
Notes:
1 The amplitude of Vbe Vi , but capacitor C 1 has prevented the 0V
level of the signal generator from altering the transistor bias V BE.
2 Observe that vce and hence output voltage vo is phase-inverted (is
antiphase to) the input signal vi.
3 The amplitude of the output vo vce , and capacitor C 2 has
prevented the quiescent d.c. level VCE from being connected to the
output terminals.
With reference to Note 2 above, the reason for the phase inversion is
explained as follows. The potential at the collector depends upon the
value of current flowing through RC. From Fig. 10(d) it can be seen
that I C goes more positive in the first half cycle, in response to the input
signal. This will result in a larger p.d. across R C , but since the upper
end of this resistor is tied to VCC , then the potential at the collector
end must fall. Thus during this half cycle v ce will decrease from its
quiescent value. In the next half cycle ic decreases, so the potential at
the collector rises and we have phase inversion.
With R C in the amplifier circuit an output voltage has been developed.
Consider now how we can utilise this so as to analyse the performance
of the amplifier. Firstly let us apply Kirchhoff ’s voltage law between
the power supply rails ( V CC and 0V), taking the route through RC and
the transistor, for the circuit of Fig. 9.
V I R V
I V V
V
CC C C CE CE CC
C
volt
when ; then volt [ ]
when
C 0 ……………^1
CC C
CC C
I
V
R
0 ; then amp ……………[ ] 2
The conditions where IC 0 and VCC 0 are two points on the axes of
the transistor’s output characteristics, and the straight line joining these
two points is known as the d.c. or static load line for resistor RC. A
typical set of characteristics with the d.c. load line drawn on it is shown
in Fig. 11. The slope of the load line is 1/ RC mA/V. The minus sign
is due to the negative slope.
Where the load line intersects the characteristic for I BQ gives the Q
point for the transistor. Indeed this gives an alternative method for
determining a suitable Q point without having to refer to the input
characteristic. Bearing in mind that VCEQ needs to be VCC /2 volt, then
the nearest intersection that corresponds to this requirement will be a
suitable choice.
The intersections of the load line with the characteristics shows the
limitations imposed on the excursions of collector current ( I c ) and
voltage ( V ce ) for a given excursion of base current ( Ib ). From this
we can determine the amplifi er current and voltage gains, which are
defi ned as follows.
the VCC rail is directly connected to the 0V rail. Thus the upper ends
of both RB and RC are effectively connected to the common 0V rail. The
a.c. equivalent circuit will therefore be as shown in Fig. 12.
Worked Example 3
Q For the amplifier circuit of Fig. 1 3 an input signal of 300 mV pk-pk causes the base current to vary by
80 μ A pk-pk about its quiescent value of 60 μ A. The output characteristics for the transistor are given in Fig. 1 4. Draw the load line on these characteristics and hence determine (a) the transistor current gain, h (^) FE, (b) the amplifier current gain, Ai , (c) the amplifier voltage and power gains, Av and A (^) p, and (d) sketch the a.c. equivalent circuit.
Vi RB Vbe (^) e
RC
c
VceVo
b
Fig. 12
VCC
RB
Vi
C 1
C
Vo
RC
82 kΩ 2.2^ kΩ
Fig. 13
A
Vi 0.3V pk-pk; I b 80 10 ^6 A pk-pk; I BQ 60 10 ^6 A; VCC 9V; R (^) C 2.2 103 ; R (^) B 82 103 For the load line: VCC I CR (^) C VCE volt
when ; V [ ]
when amp
I
I
C CE CC
CE C CC C
V V
V V
R
. 1 mA …………[ ]
Joining these two points by a straight line gives the load line as shown in Fig. 14 and its intersection with I B 60 μA gives the Q point, with VCEQ 4.6V.
6
C (mA)
5 4 3 2 1 0
2 4 6 8 10
B ^100
μA
b ^80
μA
B ^40 μA
B ^20 μA
B ^60 μ
A^ ^ BQ δC (for hFE) δC (for Ai)
δVCE VCE (V)
VCEQ
Q
Fig. 14
(a) (^) h V
h
FE C B
CE
F
^
I
I
(with V) (^ ) ( )
4 6 3 95^ 0 55^0
3
. (^6)
EE ^ 42 5.^ Ans
(b) For amplifi er gains, the excursions of I c and Vce are determined by the intercepts with the load line.
I
I
I
I
c b
i c b
A
( ) mA mA pk-pk A pk-pk
μ 773 10 80 10 34
3 6
A (^) i. 1 Ans Note that this figure is hFE.
(c)
V
V
A V
V
ce be
V ce be
( ) V V pk-pk V pk-pk
A
A A A
A
V p i V p
Ans
Ans
6 5 4 3 2 1 0
2 4 6 8 10
VCE (V)
Q
C (mA)
B^ ^100
μA
b ^80
μA
B ^40 μA
B ^20 μA
B ^60
μA^ ^ I^ BQ
δVCE
d.c. a.c.
δC
Fig. 17
a.c. load line: R R R e (^) R R C L C L
ohm 1 k 1
R (^) e 1 .8 k and the slope ^1
mA/V 0 56mA/V
Now we know that the a.c. load line will pass through the Q point; so starting at this point, if we drop vertically by 0.56 mA and then move to the right by 1 V, we will have a second point through which the a.c. load line passes. However, this second point is very close to the Q point, so to improve the accuracy, double up the above figures, i.e. starting at the Q point drop down 1. 1 2 mA and move right 2V. The resulting a.c. load line will then be plotted as in Fig. 1 7 , and the excursions of I c and Vce determined from the intersections with it, as follows.
I
I
I
C
i c b
A
A
( 3 45 0 6) mA 2 85mA pk-pk 2 85 0 80 0
3 6
ii ^ 35 6.^ Ans
V
A V
V
A
ce
V ce be V
( 7 2 2) V 4 9V pk-pk 4 9 0 3 6 3
1 Ans
A A A A
p i V p
Ans
8 Three-resistor-biased Amplifier Circuit
When this circuit is employed there will be implications for both the
d.c. and the a.c. load lines. A typical circuit is shown in Fig. 18, where
an external load resistor is also included.
d.c. load line : applying Kirchhoff’s voltage law as before:
V I R V I R
I I
V I R V I R
CC C C CE E E C E CC C C CE C E
volt
but , so
and,
when ; (as before).....
V I R V
I V V
CC C C E CE C CE CC
R
0.... [ ]
when
amp........
V 0 I
V
CE C R
CC C E
R
.. .[2]
vi
B ib
C ic
E ie
C (^1) ib
C 2
RE C^3
E
R
VCC
RC
R 2 RL
ic
ie vo
Fig. 18
The d.c. load line will now have a slope of 1/( RC RE ) volt/amp, and
when plotted on the output characteristics will establish the Q point.
a.c. load line : the effective a.c. load, R
R R
e R R
C L C L
ohm
and the a.c. load line will have a slope 1/ Re amp/volt, passing
through the Q point, as in the previous example.
The a.c. equivalent circuit is shown in Fig. 19.
vi
ib
R 1 R
RC RL
ie
ic
vo
Fig. 19
(b) (^) a.c. load line: ohm k
k
R R R
R R
R
e C^ L C L e
slope ^1 mA/V mA/V (use 1 mA/ V) 2 48
and the load line is plotted with this slope passing through the Q point as shown.
I I
I
b B c
μ A pk-pk about μA so, (.. ) mA 1. mA pkk-pk
A
A
i c b i
I
I
3 6 Ans
9 FET Small-signal Amplifier
A typical FET signal amplifi er circuit is shown in Fig. 21.
Vi VS
Vo
VDS
RS
RD R 1
D
VD
VDD
C
C
R 2
RG (^) RL
Fig. 21
The amplifier voltage gain, Av , may be determined from load lines
plotted on the output characteristics in a similar manner to that for the
BJT amplifier.
d.c. load line : VDD V D VDS VS volt
where and volt
( ) volt
when
V I R V I R
V I R R V
I
D D D S D S DD D D S DS D
0 0; V V
V
DS DD
DS
................. .[1]
when
0 ; I 2 ]
V
DS R R
DD D S
amp.......... [
Thus the d.c. load line may be plotted and a suitable Q point selected.
a.c. load line : the effective a.c. load, R
R R
e R R
D L D L
ohm
and this load line will have a slope of 1 /R e amp/volt.
Both load lines are shown plotted on Fig. 22.
D (mA)
O
VDSQ
VGSQ
VDD
VPS (V)
δVds
Q
d.c. a.c.
Fig. 22
Worked Example 6
Q The FET used in the circuit of Fig. 23 has characteristics as shown in Fig. 24.
(a) From the characteristics, determine: (i) the mutual conductance, gm , when VDS 1 2V, and (ii) the drain-source resistance, rDS for VGS 3.5 V.
Vi RS 330 Ω
3.7 kΩ
RB R1^1 kΩ
C
C C 1
R
RG RL
Fig. 23
