Download Midterm 2 Exam Questions from EECS 141 Fall 1992 - Logic Gates and Dynamic Circuits and more Exams Electrical Engineering in PDF only on Docsity!
EECS 141: Fall 1992 - MIDTERM 2
J.M. Rabaey
For all the problems, you can assume the following transistor parameters:
NMOS:
VTn = 0.75V, Kn = 20 uA/V^2 , LAMBDA = 0.05, GAMMA = 0.5 V1/2^ , 2PHI (^) F = -0.6V
PMOS:
VTp = -0.75V, Kp = 7 uA/V^2 , LAMBDA = 0.1, GAMMA = 0.5 V1/2^ , 2PHIF = -0.6V
NPN: BF = 100, VBE(on) = 0.7V, VBE(sat) = 0.8V, VCE(sat) = 0.1V, IS = 10-17A
For all problems, you may assume that the MOS transistor lengths indicated are the effective lengths (Leff) or, equivalently, that LD = 0.
Problem 1: Logic Gates
The circuits shown below have a major problem. For each of those circuits,
a). Determine its logic function. b). Explain the problem. c). Redraw the circuit such that the problem is solved. Try to keep the number of changes minimal (e.g. if a circuit is dynamic, keep it such). Also, stick to the available input signals.
Circuit 1:
a). Logic function:
A B X OUT
OUT = or OUT = (depending on what you want "?" to be)
b). The problem:
Node X is not driven by input when B=0 A=1, so X will keep its previous value. Need to make sure X is driven by one and only one input at all times.
c). Redrawn Circuit:
Want RPMOS >> R (^) NMOS + R (^) NMOSB + RNMOSC --> 1/(up) x 1/(W/L|p) >> 3/(un x W/L|n ) un /up ~ 1.8/2. --> W/L|p << W/L|n so say W/L|p = 1.8/2. Ideally, we'll set the ratio to make VOL < VTn
Note: It is true that tPHL and tPLH are asymmetric, but this is almost always true for pseudo NMOS. It is not correct to set RPMOS = RNMOSCHAIN because then VOL = V (^) DD/2.
c). Redrawn Circuit:
Problem 2: Differential Current Mirror Logic
A differential CML gate is shown below.
a). Determine the important points of the VTC (VOH, VOL, VIH, VIL and VM). For the computation of
VIH and VIL, you can use the simplified definition (V (^) IL is defined as the point where the transistor Q1 is
carrying 1% of the current through the current source, while at VIH transistor Q1 carries 99% of the total
current).
V (^) OH, VOL: Assume the current in Q1 and Q2 is IEE or zero. Current = 0 --> VOH = V (^) CC = 0 Current = IEE --> VOL = VCC - IEE RC = -0.30V
VM : This is a symmetric differential circuit, so VM = (VOL + VOH) / 2 = -0.1V
VIH , VIL: Remember, this isa differential circuit, so In and In changes. When VIn - VIn = 120mV, IC1 = 100 IC
So, VIH = VM + 60mV = -0.09V VIL = VM - 60mV = -0.21V
b). Assume that the output Out connects the input terminal of 5 identical gates (or has a fanout of 5). Recompute the values of V (^) OH and VOL under these conditions.
a). Is this circuit going to work under all conditions? If not, explain why and give a case when this circuit is not going to work.
No. If inputs are high during precharge, the output will fail to precharge to V (^) DD. (Why would inputs be high during precharge? Well, if you use "BDL" in domino or np CMOS, that could happen.)
b). Given the set of input waveforms, shown on the next page, draw the voltage waveforms for both the intermediate node X and output Out. Both have an initial value of 0V. Determine the voltage levels precisely and mark them on the drawing. You may assume that all input signals change abruptly. All capacitances have been lumped and their values have been annotated on the Figure above. To compute the transient response, you may assume that all transistors (NMOS and PMOS) can be modeled as linear resistors with a value of 15kOhm. Assume that CGS and CGD = 0 for all transistors.
Vout(2nsec) = 4.
Vout (3nsec) = 4.
Vout (7nsec) = 3.
t = 1ns -> 2ns: 40fF charging through PMOS at Out; no charge at X (floating) Vout = 5(1 - exp(- (t-1ns)/(15kOhm x 40fF) ) ) Vout(2ns) = 5(1 - exp(-1ns/0.6ns) = 4.
t = 2ns -> 3ns: Output floating -> no change in voltage X tied to ground -> no change in voltage.
