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The concept of memory hierarchy in computing systems, focusing on the use of cache memory. It discusses the different types of computer memory, including RAM and ROM, and their variations such as SRAM, DRAM, EPROM, EEPROM, and flash memory. The document also introduces the concept of locality of reference and how it is used to improve memory access times through cache memory. It explains the functioning of cache memory, its different levels, and mapping schemes.
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Q1: Why are there so many different types of computer memory?
Processors tend to access memory in a very patterned way. If memory location X is accessed at time t , there is a high probability that memory location X + 1 will also be accessed in the near future. This clustering of memory references into groups is an example of locality of reference.
When a miss is processed, instead of simply transferring the requested data to a higher level, the entire block containing the data is transferred. Because of locality of reference, it is likely that the additional data in the block will be needed in the near future, and if so, this data can be loaded quickly from the faster memory.
There are three basic forms of locality: Temporal locality — Recently accessed items tend to be accessed again in the near future. Spatial locality — Accesses tend to be clustered in the address space (for example, as in arrays or loops). Sequential locality — Instructions tend to be accessed sequentially.
The locality principle provides the opportunity for a system to use a small amount of very fast memory to effectively accelerate the majority of memory accesses.
on the processor, whereas L2 cache resides between the CPU and main memory. L1 cache is, therefore, faster than L2 cache.
Cache Mapping Schemes
So, how do we use fields in the main memory address?
Direct Mapping of Main Memory Blocks to Cache Blocks
If main memory blocks 0 and 10 both map to cache block 0, how does the CPU know which block actually resides in cache block 0 at any given time?
The answer is that each block is copied to cache and identified by the tag (see the Figure)
There are two valid cache blocks. Block 0 contains multiple words from main memory, identified using the tag “00000000”. Block 1 contains words identified using tag “11110101”. The other two cache blocks are not valid. To perform direct mapping, the binary main memory address is partitioned into the fields shown in the Figure.
The size of each field depends on the physical characteristics of main memory and cache. The word uniquely identifies a word from a specific block. This is also true of the block field—it must select a unique block of cache. The tag field is whatever is left over. When a block of main memory is copied to cache, this tag is stored with the block and uniquely identifies this block.
Consider the following example: Assume memory consists of 2^14 words, cache has 16 blocks , and each block has 8 words. From this we determine that memory has 2^14 /2^3 = 2^11 blocks. We know that each main memory address requires 14 bits. Of this 14-bit address field, the rightmost 3 bits reflect the word field (we need 3 bits to uniquely identify one of 8 words in a block). We need 4 bits to select a specific block in cache, so the block field consists of the middle 4 bits. The remaining 7 bits (2^11 /24 (16 block)= 2^7 (128) ) make up the tag field. The fields with sizes are illustrated in Figure.