unity gain high-pass - Electronic Engineering - Exam, Exams of Electrical Engineering

Main points of this exam paper are: Unity Gain High-Pass, Input Offset Voltage, Bandwidth, Magnitude, Inverting Amplifier, Feedback Resistor, Maximum Possible Output

Typology: Exams

2012/2013

Uploaded on 03/31/2013

parbarti
parbarti 🇮🇳

4.8

(9)

71 documents

1 / 6

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Cork Institute of Technology
Bachelor of Engineering in Electronic Engineering Stage 3 / Autumn 2005 Page 1 of 6
Bachelor of Engineering in Electronic Engineering – Award
(National Diploma in Engineering in Electronic Engineering – Award)
(NFQ – Level 7)
Autumn 2005
Electronic Engineering
(Time: 3 Hours)
Answer any 5 questions – 20 marks each.
Maximum available marks is 100.
Examiners: Mr. P. Collins
Mr. J. Berry
Dr R. O’Dubhghaill
p=10-12 , n=10-9 , µ=10-6 ,m=10-3 , k=103 , M=106
Q1.
An AD741 has the following specifications:
At 25°C the input offset voltage is VIO = 5mV , the input bias current is IB = 100nA and the
input offset current is IIO = 9nA. VIO/T = 15µV/°C , IB/T = 700pA/°C. AOL=106dB.
The unity gain bandwidth is UGB = 1.2MHz. The slew rate is SR = 0.5 V/µs.
(a) Draw the frequency response of the magnitude of the open loop gain. Clearly identify the
break frequency , the unity gain bandwidth and the slope of the roll-off. [ 4 marks ]
(b) The AD741 is configured as an inverting amplifier. The amplifier is required to have a
closed loop bandwidth ( fCL ) of at least 20kHz. If the feedback resistor ( Rf ) = 47k then
work out the range of the other resistor ( R1 ). [ 4 marks ]
(c) If R1=1k , then what is the maximum value of a sine wave at 5kHz that can applied before
slew rate limiting starts to take place? [ 4 marks ]
(d) If R1=1k then what is the maximum possible output error voltage due to input offset
voltage and input bias current effects at 25°C? If a balance resistor is used to reduce the
output error voltage then what should this resistor value be and what will be the percentage
reduction in the original error voltage? [ 4 marks ]
(e) If the temperature rises to 55°C then what is the new output maximum possible output error
voltage (with no balance resistor )? [ 4 marks ]
pf3
pf4
pf5

Partial preview of the text

Download unity gain high-pass - Electronic Engineering - Exam and more Exams Electrical Engineering in PDF only on Docsity!

Bachelor of Engineering in Electronic Engineering – Award

(National Diploma in Engineering in Electronic Engineering – Award)

(NFQ – Level 7)

Autumn 2005

Electronic Engineering

(Time: 3 Hours)

Answer any 5 questions – 20 marks each. Maximum available marks is 100.

Examiners: Mr. P. Collins Mr. J. Berry Dr R. O’Dubhghaill

p=10 -12^ , n=10 -9^ , μ=10 -6^ ,m=10 -3^ , k=10 3 , M=10 6

Q1. An AD741 has the following specifications: At 25°C the input offset voltage is VIO = 5mV , the input bias current is I (^) B = 100nA and the input offset current is I (^) IO = 9nA. (^) ∆V (^) IO /∆T = 15μV/°C , (^) ∆I (^) B /∆T = 700pA/°C. AOL=106dB. The unity gain bandwidth is UGB = 1.2MHz. The slew rate is SR = 0.5 V/μs.

(a) Draw the frequency response of the magnitude of the open loop gain. Clearly identify the break frequency , the unity gain bandwidth and the slope of the roll-off. [ 4 marks ]

(b) The AD741 is configured as an inverting amplifier. The amplifier is required to have a closed loop bandwidth ( fCL ) of at least 20kHz. If the feedback resistor ( Rf ) = 47kΩ then work out the range of the other resistor ( R1 ). [ 4 marks ]

(c) If R1=1kΩ , then what is the maximum value of a sine wave at 5kHz that can applied before slew rate limiting starts to take place? [ 4 marks ]

(d) If R1=1kΩ then what is the maximum possible output error voltage due to input offset voltage and input bias current effects at 25°C? If a balance resistor is used to reduce the output error voltage then what should this resistor value be and what will be the percentage reduction in the original error voltage? [ 4 marks ]

(e) If the temperature rises to 55°C then what is the new output maximum possible output error voltage (with no balance resistor )? [ 4 marks ]

Q2.

(a) A sensor has an ac output of ± 0.1V with a DC offset of –0.3V. Design a circuit using a single supply op-amp operating off +5V to produce an output signal of ±1.5V with a DC offset of 2.5V. An input of –0.4V should produce an output of 4V and an input of –0.2V is to produce an output of 1V. Assume that ac coupling is not an option. Comment on any assumptions you make. [ 10 marks ]

Vin Vout

R

R

+15V

Vref

-15V

FIGURE 1.

(b) In the circuit in Fig 1 , R2 = 15kΩ , R1 = 10kΩ , Vref = 5V. Assume that the op-amp saturates at +/- 15V. Find UTL , LTL and the hysteresis for the circuit. [ 5 marks ]

(c) Repeat part (b) but with Vref = 0V. [ 5 marks ]

Q3. (a) Draw the circuit diagram of a 1st^ order band pass filter. Derive the transfer function of the filter. What are the values of the lower and upper cutoff frequencies? [ 10 marks ]

(b) Design a unity gain high-pass Sallen-Key filter with fO = 2.5kHz and Q = 3. The resistor and capacitor values have to be standard decade values of any tolerance. What are the final Q and f (^) O for the component values you chose? Include the circuit diagram of the filter in your answer. The standard decade values are given in Fig 2. [ 10 marks ]

Q.

Vin

Vout

RC

VCC

R (^1)

R 2 R (^) E C (^) E RL

C (^) IN

C (^) OUT

R (^) S

FIGURE 3.

For the circuit shown in Fig 3 , Vcc = 15V , RS = 600Ω , R 1 = 18kΩ , R 2 = 22kΩ , RC = 1.8kΩ , RE = 2.7kΩ , RL = 2.7kΩ , C (^) IN = 2.2μF , CE = 10μF and COUT = 4.7μF. The transistor has β = 100 , CBC = 2pF and C (^) BE = 4pF. Calculate : (a) the 3 low cutoff frequencies [ 9 marks ] (b) the input Miller capacitance [ 3 marks ] (c) the output Miller capacitance [ 2 marks ] (d) the 2 high cutoff frequencies. (^) [ 6 marks ]

Q6.

FIGURE 4.

(a) Two identical MOSFETs are connected in the current mirror configuration as shown in Fig 4. The supply voltage VDD = 6V and R = 20kΩ. For each MOSFET Vt = 2V and k = 20μA/V^2. Determine the source current I (^) D1 when the circuit is functioning as a current mirror. Determine the minimum load voltage for which this source current will flow. [ 12 marks ]

(b) Show how an n-channel MOSFETs can be configured as a resistor and compare it’s IV curve to that of a resistor. [ 4 marks ]

(c) A MOSFET has k = 55.2μA/V 2 and Vt = 1V. It is configured as a resistor. What is the equivalent resistance for VDS = 2V and VDS = 3V? [ 4 marks ]