Using SAT based Image Computation for Reachability Analysis
Introduction
Model checking is a common method used in formal verification. The paper focuses on
the sub-problem: reachability analysis. The definition of image computation here is
computing the set of states reachable in one step from a given set of states under a
transition relation. Generally, Binary Decision Diagrams (BDDs) are used to
symbolically represent the set of states. The paper uses a complete SAT based method to
compute image, and does not use BDDs at all. In particular, the algorithm does not have
BDD size explosion surprises and deteriorates in a predictable manner.
Main idea
The algorithm uses SAT checkers like Chaff to read propositional formulas represented
in conjunctive normal forms (CNFs). The authors assume the states and the transition
relation are already represented in as a set of CNF clauses. It is customary to convert any
transition relation represented as a set of propositional formula to CNF form by
introducing intermediate variable. This translation is polynomial in the size of the
original circuit.
The formula Si-1(x) ∧T(x,i,x’) ∧¬Sreach(x’) can express the core of basic algorithm. This
formula ask the SAT checker to compute a satisfying assignment such that a present state
vaiable x and input variables i satisfy the predicate Si-1(x) ∧T(x,i,x’), i.e., the set of states
reachable from the newly discovered states in the previous iteration. SAT check can
compute only the states that have not seen so far by conjoining the predicate mentioned
above with the negation of the set of all accumulated states so far ( ¬Sreach(x’)).
Furthermore, the paper fixes out two key problems, which cause the above basic
algorithm inefficient and impractical. First, the paper considers the advantage of
situation: only a partial assignment to all variables satisfies the clause database given to
SAT. A partial assignment to x’ describes more than one state at a time, the larger the set
the few the number of assignments. The use of advantage can prune the number of set
enumerations drastically. Second, the paper use a hash table, each entry of which contains
a trie, to store the Si and Sreach. This efficient data structure really helps to reduce the space
requirement.
Comments
The runtime of the algorithm in this paper depends on the size of input circuit and the
diameter of the circuit only, which is very meaningful. Because the traditional way BDD
based model checkers do not have a gradual degradation in performance, and the
performance is often not predictable. Furthermore, the efficiency of SAT procedures has
made it possible to handle circuits with a few variables, much larger than any BDD based
model checker is able to do at present.
