CARRY LOOK AHEAD ADDER
Verilog
Coding
module carryLookAhead(S,Cout,a,b,Cin);
input [3:0]a,b;
input Cin;
output [3:0]S;
output Cout;
wire [3:0]g,p;
wire w1,w2,w3,w4;
assign p[0] = a[0]^b[0];assign p[1] = a[1]^b[1];
assign p[2] = a[2]^b[2];assign p[3] = a[3]^b[3];
assign g[0] = a[0]&b[0];assign g[1] = a[1]&b[1];
assign g[2] = a[2]&b[2];assign g[3] = a[3]&b[3];
assign w1 = g[0]|(Cin&p[0]);
assign w2 = g[1]|(w1&p[1]);
assign w3 = g[2]|(w2&p[2]);
assign w4 = g[3]|(w3&p[3]);
assign Cout = w4; assign S[0] = p[0]^Cin;
assign S[1] = p[1]^w1; assign S[2] = p[2]^w2;
assign S[3] = p[3]^w3;
endmodule
Testbench
module carryLookAhead_TB_v;
initial begin
a=4'b1100; b=4'b0000; Cin=0; #100;
a=4'b1010; b=4'b0100; Cin=0; #100;
a=4'b1100; b=4'b0000; Cin=1; #100;
a=4'b1010; b=4'b1100; Cin=1; #100;
end
endmodule
CARRY SKIP ADDER
Carry Skip Adder Coding
module carrySkipAdder(S,Cout,a,b,Cin);
input [3:0]a,b;
input Cin;
output [3:0]S;
output Cout;
wire [3:0]p;
wire w1,bp;
rca r1(S[3:0],w1,a[3:0],b[3:0],Cin);
propagate p1(p[3:0],bp,a[3:0],b[3:0]);
mux m1(Cout,w1,Cin,bp);
endmodule
Carry Skip Adder Testbench
module carrySkipAdder_TB_v;
initial begin
a=4'b1100; b=4'b0000; Cin=0; #100;
a=4'b1010; b=4'b0100; Cin=0; #100;
a=4'b1100; b=4'b0000; Cin=1; #100;
a=4'b1010; b=4'b1100; Cin=1; #100;
end
endmodule
