vhdl solotion, Schemes and Mind Maps of Verilog and VHDL

Download vhdl solotion and more Schemes and Mind Maps Verilog and VHDL in PDF only on Docsity! 40027784 agrtils ojlak yl Cea WBS Coe GLE |) yhde Se cde plFLo 5 JS -1 ademas Ly GI VHDL asl 9 cdge ob pl Fg pg Sue CUl> 4:1, hve JS Cond a tal (ge Seed dy pj JS joe pl FL9 Sob Cle pl Sho 4 ae95 b ay 1) jbde RESET JUS io 9 995 0 jhe he 3 egy Cards ped Hel ILI2 clo 60559 Op ge 50 adel Cardy MAL ge hel Crom 99 ald oye IS aegare 2 leMbl cud -1 WS cco dbeal |, Ju Cosund gla Ly he cle 60939 Gulsl a wed coe plat) jl age SLedUb JURII jlae cheb Seedy & aegi l -b 929 G59 NB eg F 99 |) HedUbl jL5 oy90 gle} yo -€ syle Ju ceesad -2 g alaSl> (bg) 99 4 Ghd Cady 9 (LENE Cond) by cle Jikee Gulul » a ES Coe ete org F Gly |) SLEDIL! JAI igh el Foo See 5 a8 ety 2) JRO Glee cyl NS al Slo Sob Sol ply Fo 29 See G9) JET ond oly’ jo GLB SE Rae 4p (Le (cage 9 Sled! JLB! Jgde) 59 dgege GledIb! jols Cand: pm loys BS ROM cligirce Gp g shee Gels el FL9 Seb ery: ete ale ys EL coe pS Cle Crand ols g Cul ond ath F i yo ty 64 Sg ROM abail> cla ails eyed le by b Biles Hb cul ob Yasue Guyot Jase 59 aS ROM Slginns Jal ails 5 wel (ge Coos 5 JSS Gilles jlre 99,5 cle s NEXT ADDRESS = Spl plas (99j97 Come ha, ands Cau! Li ve le BRANCH 4; bg: 50 Cyndy pth (ge Aa, F Li 9s 0 absdle Goat ol SO jae cle BRANCH ciel oo Ge gl pews yo aS jgbilan aS Cu! CW(63)=CS(23) b 12 Cogy9 gaa Cords hy, bd wal Sy ply aile 63 as cooly wb pho ply NA n CuISO Glee coy ale wb oe LCS(31) = 1 byt cle opt 59 jhe Gog > WL ce pj) JRE Sygen jae CUl> pl, FL Sper VL yo ode! Coots PMG gles ROM 4 bg 0 Sledtel Lb yung, 5 illo oad ancigi VHDL aol» el JS sols Gul el 5b Lo pj library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; use IEEE.numeric_STD.all; entity CONTROL is generic(AGL_delay, MAR_delay,ROM_delay,MIR_delay:time:=0 ns); port(C:in STD_LOGIC_VECTOR(23 downto 0):= x"000000"; clk,reset: in STD_LOGIC; LCS:OUT STD_LOGIC_VECTOR(31 downto 0):= x"00000000"); end CONTROL; --use work.three_function.all architecture algorithmic of CONTROL is signal MAR,NMAR: STD_LOGIC_VECTOR(7 downto 0); signal Cword: STD_LOGIC_VECTOR(63 downto 0); signal MIR: STD_LOGIC_VECTOR(63 downto 0); signal NAD: STD_LOGIC_VECTOR(7 downto 0); signal CS: STD_LOGIC_VECTOR(23 downto 0); begin MARP: process(clk,reset) begin if reset='1' then MAR<= B"00000000" after MAR_delay; elsif clk'event and clk='0' then MAR<= NMAR after MAR_delay; end if; end process MARP; ROMP: process(MAR) type MEM_type is array(0 to 255) of STD_LOGIC_VECTOR(63 downto 0); elsif LCS(29)='1' then reg_vec <= "111"; end if; end if; end process; (23) <= 12; C(22) <=11 and not |2; C(21) <= not I1 and not 12; OUTPUT <= reg_vec; end data_flow; Ly glre Lal eb l Fo Sab Syger gre Sled! g Ju cle cond Gull .c stnle py weet oat oolatal ISE Isl pi Soiled Coon’ jl lee alySLo Spb puny Cae -DATA8 [input 1. 5 6 (23:0) FE} — [input2>———!2 elk dik: <5: L6S(34:0) i S631: UTPUT (250) FER Oy [reset reset [clock {$46 (23:0) : Ane dasegd ET Cpe 9 demegis Ly glide VHDL Jars onal os geil jf oolaut .d wep ULES Cilo yg GT Ares 9 ey Guus VHDL oS 5 Cul YL Syqeas ISE 1551 3 Sslad Cand 9 de oles Jaro LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY UNISIM; USE UNISIM.Vcomponents.ALL; ENTITY SHEMATIC_SHEMATIC_sch_tb IS END SHEMATIC_SHEMATIC_sch_tb; ARCHITECTURE behavioral OF SHEMATIC_SHEMATIC_sch_tb IS COMPONENT SHEMATIC PORT( clock, reset, input1,input2: IN STD_LOGIC; XLXN_14 : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END COMPONENT; SIGNAL clock : STD_LOGIC:= SIGNAL reset : STD_LOGIC; SIGNAL input1 : STD_LOGIC; SIGNAL input2 : STD_LOGIC; SIGNAL XLXN_14 : STD_LOGIC_VECTOR (2 DOWNTO 0); BEGIN UUT: SHEMATIC PORT MAP( clock =>clock, reset => reset, input1 => input1, input2 => input2, XLXN_14 => XLXN_14); clock <= not clock after 10 ns; tb : PROCESS BEGIN reset <='1', 'O' after 35 ns; input1 <= '0'; input2 <='0'; wait for 50 ns; input1 <= '0'; input2 <='1'; wait for 15 ns; input1 <='1'; input2 <='0'; wait for 15 ns; EL Co 2) input1 <= '1'; input2 <= ; wait for 15 ns; input1 <= '0'; input2 <='0'; wait for 15 ns; input1 <='1'; input2 <='0'; wait for 15 ns; END PROCESS; END; ce Ceendy past CLOCK aay all gil 10 jo Guy od 83,8 Ls jo 50 MHZ las SSIS: Seg! cule 4, CLOCK osig, YL ad Gadel jo yhoo m9 > 9 og) Ld Jol auld gil 35 9 RESET (6099 os geod hve CLOCK ya lily al phe ply 12 22959 2 pe 92 Tb Gal 99 99) 650 4) Ae EL G59 2) yg Gils deed Are 59999 lie clatll> Goll pp ams (92 Condy xben_1412:0