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University of California, Berkeley College of Engineering Computer Science Division ⎯ EECS
Fall 2006 John Kubiatowicz
Midterm I
October 11th, 2006 CS162: Operating Systems and Systems Programming
Your Name:
SID Number:
Discussion Section:
General Information: This is a closed book exam. You are allowed 1 page of hand-written notes (both sides). You have 3 hours to complete as much of the exam as possible. Make sure to read all of the questions first, as some of the questions are substantially more time consuming.
Write all of your answers directly on this paper. Make your answers as concise as possible. On programming questions, we will be looking for performance as well as correctness, so think through your answers carefully. If there is something about the questions that you believe is open to interpretation, please ask us about it!
Problem Possible Score
Total 100
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Problem 1e[3pts]: For each of the following thread state transitions, say whether the transition is legal and how the transition occurs or why itcannot. Assume Mesa-style monitors.
1). Change from thread state BLOCKED to thread state RUNNING
2). Change from thread state RUNNING to thread state BLOCKED
3). Change from thread state RUNNABLE to thread state BLOCKED
Problem 1f[4pts]: Consider the Dining Lawyers problem, in which a set of lawyers sit around a table with one chopstick between each of them. Let the lawyers be numbered from 0 to n-1 and be represented by separate threads. Each lawyer executes Dine(i), where “i” is the lawyer’s number. Assume that there is an array of semaphores, Chop[i] that represents the chopstick to the left of lawyer i. These semaphores are initialized to 1.
void Dine(int i) { Chop[i].P(); /* Grab left chopstick / Chop[(i+1)%n].P(); / Grab right chopstick / EatAsMuchAsYouCan(); Chop[i].V(); / Release left chopstick / Chop[(i+1)%n].V(); / Release right chopstick */ }
This solution can deadlock. Assume that it does. List the four conditions of deadlock and explain why each of them is satisfied during the deadlock:
Problem 1g[3pt]: Pick one of the above four conditions and rewrite the code to eliminate it. Identify the condition you chose carefully and explain why your code doesn’t deadlock:
Problem 1h[2pts]: The Banker’s algorithm is said to keep the system in a “safe” state. Describe what a “safe” state is and explain how the Banker’s algorithm keeps the system in a safe state. Keep your answer short.
EXTRA CREDIT
Problem 1i[2pts]: Describe what “core” memory is and how it looks.
Problem 2b[5pts]: Show how to implement the Semaphore class using Monitors (i.e. the Lock and CondVar classes). Make sure to implement all three methods, Semaphore(), P(), and V(). None of the methods should require more than five lines. Assume that Monitors are Mesa scheduled.
public class Semaphore {
public Semaphore(int initialValue) {
} public P() {
} public V() {
} } Problem 2c[3pts]: Show how to implement the Lock class using Semaphores. Make sure to implement the Lock(), Acquire(), and Release() methods. None of the methods should require more than five lines.
public class Lock {
public Lock() {
} public void Acquire() {
} public void Release() {
} }
Problem 2d[2pts]: Explain the difference in behavior between Semaphore.V() and CondVar.Signal() when no threads are waiting in the corresponding semaphore or condition variable:
Problem 2e[12pts]: Show how to implement the Condition Variable class using Semaphores (and your Lock class from 2c). Assume that you are providing Mesa scheduling. Be very careful to consider the semantics of CondVar.Signal() as discussed in (2d). Hint: the Semaphore interface does not allow querying of the size of its waiting queue; you may need to track this yourself. None of the methods should require more than five lines.
public class CondVar {
public CondVar(Lock lock) {
} public void Wait() {
} public void Signal() {
} public void Broadcast() {
} }
Synchronization technique #3: Suppose each thread does the following:
- while (TestAndSet(flag) == false)
- do nothing;
- Execute Critical Section;
- flag = false;
Problem 3e[3pts]: Will this protect the critical section? If “yes”, explain why. If “no”, explain and explain how to fix it.
Problem 3f[2pts]: Assume the above code (or your fixed version). Will this code be “fair”? Explain.
Synchronization technique #4: Suppose we have different code for each thread:
THREAD A THREAD B A1. flag_A = true; B1. flag_B = true; A2. while (flag_B == true) B2. while (flag_A == true) A3. do nothing; B3. do nothing; A4. Execute Critical Section; B4. Execute Critical Section; A5. flag_A = false; B5_._ flag_B = false;
Problem 3g[3pts]: Will this protect the critical section? If “yes”, explain why. If “no”, explain and explain how to fix it. Note that this question is only about protecting the critical section!
Problem 3h[3pts]: Explain why this code (or your fixed version) would not be a particularly good mechanism for synchronizing threads A and B. (hint: imagine that threads A and B repeatedly try to acquire the critical section). After describing the problem, explain how to fix the problem by replacing the “do nothing” with no more than three lines inside each while loop above.
Problem 4: Scheduling [20pts]
Problem 4a[2pts]: Describe one way to predict the burst runtime (time between I/O operations) for a thread.
Problem 4b[3pts]: What is priority inversion? Explain how a priority scheduler could be modified to avoid priority inversion.
Problem 4c[3pts]: Explain what a multi-level feedback scheduler is and why it approximates SRTF.
Problem 4d[2pts]: Explain how to fool the multi-level feedback scheduler’s heuristics into giving a long-running task more CPU cycles.
Problem 4f[3pts]: For each process in each schedule above, indicate the queue wait time and completion time (otherwise known as turnaround time, TRT). Note that wait time is the total time spend waiting in queue (all the time in which the task is not running), while TRT is the total time from when the process arrives in the queue until it is completed.
Scheduler Process 1 Process 2 Process 3 Process 4 Process 5 FCFS wait FCFS TRT SRTF wait SRTF TRT RR wait RR TRT
Problem 4g[2pts]: Assume that we could have an oracle perform the best possible scheduling to reduce average wait time. What would be the optimal average wait time, and which of the above three schedulers would come closest to optimal? Explain.
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Consider a multi-level memory management scheme using the following format for virtual addresses: Virtual seg # (4 bits)
Virtual Page # (8 bits)
Offset (8 bits)
Virtual addresses are translated into physical addresses of the following form:
Physical Page # (8 bits)
Offset (8 bits)
Problem 5d[4pts]: For the following Virtual Addresses, translate them into Physical Addresses. Use the Segment Table and Physical Memory table given on the next page. Segment entries point to page tables in memory. A page table consists of a series of 16 bit page table entries (PTEs). The format of a PTE is given on the next page. Briefly, the first byte of the PTE is an 8-bit physical page #, and the second byte is an 8-bit flags field with one of the following values:
0x00 (Invalid), 0x06 (Valid, RO), 0x07 (Valid, R/W).
If there is an error during translation, make sure to say what the error is. Errors can be “ bad segment error ” (undefined or invalid segment), “ segment overflow error ” (address outside range of segment), or “ access violation error ” (page invalid, or attempt to write a read only (RO) page). Two answers are given:
Virtual Addr Physical Addr Virtual Addr Physical Addr 0x10123 0x4123 0x 0x33423 Segment overflow 0x 0x20456 0x
Problem 5e[6pts]: Consider the same multi-level memory management scheme. Please return the results from the following load/store instructions. Addresses are virtual. The return value for load is an 8-bit data value or an error, while the return value for a store is either “ ok ” or an error. For errors, please specify which type of error (from the above set). Two answers are given:
Instruction Result Instruction Result Load [0x30115] 0x57 Store [0x00310] Store [0x30116] Access violation Load [0x31202] Load [0x51015] Store [0x10231] Load [0x00115] Load [0x12345]
Virtual Address Format
Virtual seg # (4 bits)
Virtual Page # (8 bits)
Offset (8 bits)
Segment Table (Max Segment=3)
Seg
Page Table
Base
Max Page
Entries
Segment
State
0 0x2030 0x20 Valid
1 0x1020 0x10 Valid
2 0x3110 0x40 Invalid
3 0x4000 0x20 Valid
Page Table Entry
First Byte Second Byte
Physical Page Number
0x00 = Invalid 0x06 = Valid, RO 0x07 = Valid, R/W
Physical Memory
Address +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
[ Scratch Sheet (Feel free to remove) ]
