CSE351, Autumn 2017L22: Virtual Memory II
VirtualMemoryII
CSE351Autumn2017
Instructor:
JustinHsia
TeachingAssistants:
LucasWotton
MichaelZhang
ParkerDeWilde
RyanWong
SamGehman
SamWolfson
SavannaYee
VinnyPalaniappan
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1) Processor sends virtual address to MMU. 2‐3) MMU fetches PTE from page table in cache/memory. 4) Valid bit is zero, so MMU triggers page fault exception.
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CSE351, Autumn 2017
L22: Virtual Memory II
Virtual Memory II CSE 351 Autumn 2017 Instructor: Justin Hsia Teaching Assistants: Lucas WottonMichael ZhangParker DeWildeRyan WongSam GehmanSam WolfsonSavanna YeeVinny Palaniappan
CSE351, Autumn 2017
L22: Virtual Memory II
Administrivia
Lab 4 due next Monday (11/27)
Homework 5 released Thursday (3/9)^
Processes and Virtual Memory
There is lecture on Wednesday^
Practice and review problems, plus fun slides on a recentVM exploit
Will be uploaded to Panopto, as usual
“Virtual Section” on Virtual Memory^
Worksheet and solutions released on Wednesday
Videos of Justin working through problems
CSE351, Autumn 2017
L22: Virtual Memory II
Review: Terminology
Context switch^
Switch between processes on the same CPU
Page in^
Move pages of virtual memory from disk to physical memory
Page out^
Move pages of virtual memory from physical memory to disk
Thrashing^
Total working set size of processes is larger than physicalmemory and causes excessive paging in and out instead ofdoing useful computation
CSE351, Autumn 2017
L22: Virtual Memory II
VM for Managing Multiple Processes
Key abstraction: each process has its own virtual address space^
It can view memory as
a simple linear array
With virtual memory, this simple linear virtual address spaceneed not be contiguous in physical memory^
Process needs to store data in another VP? Just map it to
any
PP!
Virtual
Address
Space for
Process 1:
PhysicalAddressSpace(DRAM)
0
N‐
(e.g., read‐onlylibrary code)
Virtual
Address
Space for
Process 2:
VP 1VP 2
0
N‐
VP 1VP 2
PP 2 PP 6 PP 8
0
M‐
Address
translation
CSE351, Autumn 2017
L22: Virtual Memory II
VM for Protection and Sharing
The mapping of VPs to PPs provides a simple mechanism to protect
memory and to
share
memory between processes
Sharing:
map virtual pages in separate address spaces to the same
physical page (here: PP 6)
Protection:
process can’t access physical pages to which none of its
virtual pages are mapped (here: Process 2 can’t access PP 2)
Virtual
Address
Space for
Process 1:
PhysicalAddressSpace(DRAM)
0
N‐
(e.g., read‐onlylibrary code)
Virtual
Address
Space for
Process 2:
VP 1VP 2
0
N‐
VP 1VP 2
PP 2 PP 6 PP 8
0
M‐
Address
translation
CSE351, Autumn 2017
L22: Virtual Memory II
Memory Protection Within Process
VM implements read/write/execute permissions^
Extend page table entries with permission bits
MMU checks these permission bits on every memory access
If violated, raises exception and OS sends SIGSEGV signal to process(segmentation fault)
Physical
Address Space
PP 2 PP 4 PP 6 PP 8PP 9
PP 11
Process
i
PPN
WRITE
EXEC
PP 6
No
No
PP 4
No
Yes
PP 2
Yes
No
READ
YesYesYes
VP 0:VP 1:VP 2:
YesYesYes Valid
Process
j
WRITE
EXEC
PP 9
Yes
No
PP 6
No
No
PP 11
Yes
No
READ
YesYesYes
VP 0:VP 1:VP 2:
YesYesYes Valid
PPN
CSE351, Autumn 2017
L22: Virtual Memory II
Address Translation: Page Fault
Processor sends virtual address to MMU
MMU fetches PTE from page table in cache/memory
Valid bit is zero, so MMU triggers page fault exception
Handler identifies victim (and, if dirty, pages it out to disk)
Handler pages in new page and updates PTE in memory
Handler returns to original process, restarting faulting instruction
MMU
Cache/Memory
CPU
VA
CPU Chip
PTEA
PTE
1
2 3
4
5
Disk
Page fault handler
Victim page
New page
Exception
6
7
CSE351, Autumn 2017
L22: Virtual Memory II
Hmm… Translation Sounds Slow
The MMU accesses memory
twice
: once to get the
PTE for translation, and then again for the actualmemory request^
The PTEs
may
be cached in L1 like any other memory word
But they may be evicted by other data references
And a hit in the L1 cache still requires 1‐3 cycles
What can we do to make this faster?^
Solution:
add another cache!
CSE351, Autumn 2017
L22: Virtual Memory II
TLB Hit
A TLB hit eliminates a memory access!
MMU
Cache/Memory
PA
Data
CPU
VA
CPU Chip
PTE
1
2
4
5
TLB
VPN
3
TLB
PTE
VPN
→
PTE
VPN
→
PTE
VPN
→
CSE351, Autumn 2017
L22: Virtual Memory II
TLB Miss
A TLB miss incurs an additional memory access (the PTE)^
Fortunately, TLB misses are rare
MMU
Cache/Memory
PA
Data
CPU
VA
CPU Chip
PTE
1
2
5
6
TLB
VPN
4 PTEA
3
TLB
PTE
VPN
→
PTE
VPN
→
PTE
VPN
→
CSE351, Autumn 2017
L22: Virtual Memory II
Address Translation
Virtual Address
TLB
Lookup
Page Table
“Walk”
Update
TLB
Page Fault
(OS loads page)
Protection
Check
PhysicalAddress
TLB Miss
TLB Hit
Page not
in Mem
Access
Denied
AccessPermitted
Protection
Fault
SIGSEGV
Pagein Mem
Check cache
Find in Disk
Find in Mem
CSE351, Autumn 2017
L22: Virtual Memory II
Context Switching Revisited
What needs to happen when the CPU switchesprocesses?^
Registers:
Save state of old process, load state of new process
Including the Page Table Base Register (PTBR)
Memory:
Nothing to do! Pages for processes already exist in memory/disk andprotected from each other
TLB:
Invalidate
all entries in TLB – mapping is for old process’ VAs
Cache:
Can leave alone because storing based on PAs – good for shared data
CSE351, Autumn 2017
L22: Virtual Memory II
Simple Memory System Example (small)
Addressing^
14‐bit virtual addresses
12‐bit physical address
Page size = 64 bytes
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VPO
VPN
Virtual Page Number
Virtual Page Offset
11
10
9
8
7
6
5
4
3
2
1
0
PPO
PPN
Physical Page Number
Physical Page Offset
CSE351, Autumn 2017
L22: Virtual Memory II