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Virtual Memory - programmer views memory as large address space without concerns about the amount of physical memory or memory management. (What do the terms 32-bit (or 64-bit) operating system or overlays mean?)
CPU
32
Virtual Virtual or Logical Address
Physical Memory Memory 0 MMU 1
(Memory Mgt. Unit)
Logical Addr.
Physical. Addr.
(50 ns access)
3 ms + 9 ms + 0.5 ms = 12.2 ms (rot.) (seek) (transfer) (12,200,000 ns average access)
Benefits :
- programs can be bigger that physical memory size since only a portion of them may actually be in physical memory.
- higher degree of multiprogramming is possible since only portions of programs are in memory
Operating System’s goals with hardware support are to make virtual memory efficient and transparent to the user.
Lecture 22 Page 1
Memory-Management Unit (MMU) for paging
CPU
Physical Memory
page 0
page 0 page 3
page 3
page 1
page 1 page 4
page 4
page 2
page 2 page 5
page 5
page 6
page 6
Process A
Process B
Frame Number
page 3 of A
page 5 of B
page 2 of A page 4 of B
page 5 of A
page 2 of B
page 0 of A
page# offset frame# offset 5 50 50
Running Process A (^) Frame#
Valid Bit 0 1 2 3 4 5 6 1 0 1 1 0 1 0 4 - 5 1 - 2 -
Page Table for A
Logical Addr. Physical Addr.
Demand paging is a common way for OSs to implement virtual memory. Demand paging (“lazy pager”) only brings a page into physical memory when it is needed. A “Valid bit” is used in a page table entry to indicate if the page is in memory or only on disk.
A page fault occurs when the CPU generates a logical address for a page that is not in physical memory. The MMU will cause a page-fault trap (interrupt) to the OS.
Steps for OS’s page-fault trap handler:
Check page table to see if the page is valid (exists in logical address space). If it is invalid, terminate the process; otherwise continue.
Find a free frame in physical memory (take one from the free-frame list or replace a page currently in memory).
Schedule a disk read operation to bring the page into the free page frame. (We might first need to schedule a previous disk write operation to update the virtual memory copy of a “dirty” page that we are replacing.)
Since the disk operations are soooooo slooooooow, the OS would context switch to another ready process selected from the ready queue.
After the disk (a DMA device) reads the page into memory, it involves an I/O completion interrupt. The OS will then update the PCB and page table for the process to indicate that the page in now in memory and the process is ready to run.
When the process is selected by the short-term scheduler to run, it repeats the instruction that caused the page fault. The memory reference that caused the page fault will now succeed.
Lecture 22 Page 2
Fortunately, programs exhibit locality of reference that helps achieve low page-fault rates
spatial locality - if a (logical) memory address is referenced, nearby memory addresses will tend to be referenced soon.
temporal locality - if a memory address is referenced, it will tend to be referenced again soon.
Typical Flow of Control in a Program
page boundaries
Virtual Addr. Space
"Text" segment of Virtual Addr. Space
"Data" segment of
Run-Time Stack
Global Data
for i :=
end for
i:
Data references within the loop
page 5
page 6
page 7
page 8
page 101
page 102
page 103
page 100
a locality
a locality
of
of
reference
reference
Possible reference string: 5, ( 5, 101, 5, 5, 5, 101, 5, 5, 5, 100, 5, 103, 6, 6, 6 ), 6, 6, 6,
6, 7, 7, 7, 7, (7, 7, 103, 7, 101, 7, 7, 7, 101, 7, 8, 8, 8, 100, 8), 8, 8, ...
n 2n
Terms: reference string - the sequence of page #’s that a process references
locality - the set of pages that are actively used together
working set - the set of all pages accessed in the current locality of reference
Lecture 22 Page 4
Storage of the Page Table Issues
- Where is it located? If it is in memory, then each memory reference in the program, results in two memory accesses; one for the page table entry, and another to perform the desired memory access.
Solution: TLB (Translation-lookaside Buffer) - small, fully-associative cache to hold PT entries Ideally, when the CPU generates a memory reference, the PT entry is found in the TLB, the page is in memory, and the block with the page is in the cache, so NO memory accesses are needed. However, each CPU memory reference involves two cache lookups and these cache lookups must be done sequentially, i.e., first check TLB to get physical frame # used to build the physical address, then use the physical address to check the tag of the L1 cache.
Alternatively, the L1 cache can contain virtual addresses (called a virtual cache ). This allows the TLB and cache access to be done in parallel. If the cache hits, the result of the TLB is not used. If the cache misses, then the address translation is under way and used by the L2 cache.
- Ways to handle large page tables: Page table for each process can be large e.g., 32-bit address, 4 KB (2^12 bytes) pages, byte-addressable memory, 4 byte PT entry
Page # Offset
20 bits 12 bits
1 M (2^20 ) of page table entries, or 4MB for the whole page table with 4 byte page table entries
Solutions: a) two-level page table - the first level (the "directory") acts as an index into the page table which is scattered across several pages. Consider a 32-bit example with 4KB pages and 4 byte page table entries.
Page # Offset
20 bits 12 bits
10 bit directory index
10 bit page offset
First 1 K entries of the page table
Second 1 K entries of the page table
Frame#
Valid Bit
Directory Page
Frame# Offset Physical Addr.
Virtual Addr.
Lecture 22 Page 5
Design issues for Paging Systems Conflicting Goals:
Want as many (partial) processes in memory (high degree of multiprogramming) as possible so we have better CPU & I/O utilization eallocate as few page frames as possible to each process
Want as low of page-fault rate as possible eallocate enough page frames to hold all of a process’ current working set (which is dynamic as a process changes locality)
Degree of Multiprogramming
CPU Utilization
so many processes in memory that not enough page frames are allocated to each process to hold their current working set of pages
Thrashing occurs when processes spend more time in page fault wait than doing useful work
Operating systems need to have
- frame-allocation algorithm to decide how many frames to allocate to each process
- page-replacement algorithm to select a page to be removed from memory in order to free up a page frame on a page fault
Page-Replacement Algorithm - selects page to replace when a page fault occurs Reasonable page-replacement algorithms must
- not be too expensive to implement w.r.t. time, hardware, or memory
- have good phase transition - “forget”/replace pages of the old locality of reference when the program moves on to a new locality of reference.
Possible Page-Replacement Algorithms: A. FIFO
9 page faults Page fault rate = 9/
Page Frames 1* 2* 3* 4* 1* 2* 5* 5 5 3* 4* 4 Allocated = 3
References 1 2 3 4 1 2 5 1 2 3 4 5 String:
Lecture 22 Page 7
What if we allocate more page frames? What would we expect to happen to the page fault rate?
10 page faults Page fault rate = 10/
Page Frames Allocated = 4
References 1 2 3 4 1 2 5 1 2 3 4 5 String:
We increased the number of page frames allocated and the page fault rate got worse !!! Belady’s anomally (IBM) - this does not usually happen with FIFO, but it can.
B. Optimal Page Replacement Algorithm - select page that’s not needed for the longest time in the future (impossible to actually implement)
This is the best we can do with 3 page frames allocated. Optimal algorithm does not suffer from Belady’s anomally.
7 page faults Page fault rate = 7/
Page Frames 1* 2* 3* 4* 4 4 5* 5 5 5 5 5 Allocated = 3
References 1 2 3 4 1 2 5 1 2 3 4 5 String:
C. LRU (Least Recently Used) - uses principle of locality to approximate the optimal algorithm
LRU does not perform well for this string, but in general you can construct a reference string to make a page-replacement algorithm look bad (except for optimal alg.) In general LRU is a good page-replacement algorithm.
10 page faults Page fault rate = 10/
Page Frames 1* 2* 3* 4* 1* 2* 5* 1 2 3* 4* 5* Allocated = 3
References 1 2 3 4 1 2 5 1 2 3 4 5 String:
Lecture 22 Page 8
B. Second-Chance/Clock Replacement - only store one counter/history bit per page-table entry For the pages in memory, maintain a circular FIFO queue of pages
next victim pointer
On a page fault, the pointer is moved until a page with a reference bit of 0 is found. This page is selected to be replaced. While the pointer is being moved, reference bits are cleared. As the pointer moves it leaves a trail of 0s in its wake. If one of these pages is referenced be for the pointer returns, it gets a "second change" and can remain in memory.
State Before Selecting Page
next victim pointer
State After Selecting Page
Page Selected for Replacement
Trail of 0s from advancing pointer
C. Not Recently Used (NRU) / Enchanced Second-Chance Algorithm - in addition to the a single reference bit, use the modified/dirty bit to decide which page to replace. On a page fault, the OS splits pages in memory fall into the following four categories based on their reference and modify bits.
- Not referenced and not modified
- Not referenced and modified
- Referenced and not modified
- Referenced and modified Prefered pagesto replace
(^) Less I/O if page is not modified
Lecture 22 Page 10
Frame-Allocation Algorithms - to decide how many frames to allocate to each process Goal: Allocate enough frames to keep all pages used in the current locality of references without allocating too many page frames. The OS might maintain a pool of free frames in a free-frame list.
Allocation Policies:
local page replacement - When process A page faults, consider only replacing pages allocated to process A. Processes are allocated a fixed fraction of the page frames.
global-page replacement - When a page fault occurs, consider replacing pages from any process in memory. Page frames are dynamically allocated among processes, i.e., # of page frames of a process varies. Advantage: as a process’ working set grows and shrinks it can be allocated more or less page frames accordingly. Disadvantage: a process might be replacing a page in the locality of reference for another process. Thrashing is more of a problem in systems that allow global-page replacement.
Implementation of global-page replacement a) Page-Fault Frequency - OS monitors page-fault rate of each process to decide if it has too many or not enough page frames allocated
Number of Page Frames Allocated
Page-Fault Rate Too many page frames allocated
Desired operating range
Too few page frames allocated
(Page-fault rate for an individual process)
Additionally, free frames could be allocated from the free-frame list or removed from processes that have too many pages. If the free-frame list is empty and no process has any free frames, then a process might be swapped out.
Lecture 22 Page 11
Problems with Segmentation:
- hard to manage memory efficiently due to internal fragmentation
- segments can be large in size so not many can be loaded into memory at one time
Solution: Combination of paging with segmentation by paging each segment.
CPU
seg.# offset 3 1034
Running Process X
Valid Bit 0 1 2 3 4 5 6 1 1 1 1 1 0 0
Segment Table for X
Logical Addr.
Physical Memory
Frame Number
page 0 of seg 0
page 4 of seg 4
page 2 of seg 4 page 0 of seg 1
page 0 of seg 3
page 3 of seg 4
page 1 of seg 3
Pointer to Page Table
frame# offset
Frame#
Frame#
Frame#
Frame#
Valid
Valid
Valid
Valid
Bit
Bit
Bit
Bit
Page Table for Seg. 0
Page Table for Seg. 1
Page Table for Seg. 2
Page Table for Seg. 3
Physical Addr.
page offset
Lecture 22 Page 13
