Download Understanding Virtual Memory: Swapper & Page Replacement Algorithms - Prof. Ingrid Hybinet and more Study notes Operating Systems in PDF only on Docsity!
Maria Hybinette, UGA
CSCI 4730
Operating Systems
Virtual Memory
Maria Hybinette, UGA^2
Chapter 10: Virtual Memory
Questions?
! What is virtual memory and when is it useful?
! What is demand paging?
! When should pages in memory be replaced?
! When should pages be put on disk?
! What is the working set model?
Maria Hybinette, UGA^3
Operating System!s Goals
! Support processes when there is not enough
physical memory
» Single process with very large address space
» Multiple processes with combined address spaces
! User code should be independent of amount
of physical memory
» Correctness, if not performance
Maria Hybinette, UGA^4
Idea: Virtual Memory
! OS provides an illusion of
more memory than is
physically available:
» Large logical space but
really
» small physical memory
! Why does this work?
» Only part of the program
needs to be in memory (at a
particular time) for execution
» Relies on key properties of
user processes (workload)
and machine architecture
(hardware)
Maria Hybinette, UGA^5
Observations
! Sequential memory accesses of a process are
predictable and tend to have locality of reference :
» Spatial: reference memory addresses near previously
referenced addresses (in memory)
» Temporal: reference memory addresses that have
referenced in the past
! Processes spend majority of time in small portion
of code
» Estimate: 90% of time in 10% of code
! Implication:
» Process only uses small amount of address space at any
moment
» Only small amount of address space must be resident in
physical memory
Maria Hybinette, UGA^7
Approach: Demand Paging
! Bring in pages into
memory only when needed
» Less memory
» Less I/O
» Faster response time
! Process viewed as a
sequence of pages rather
than contiguous address
space
» Pager (whole process)
» Swapper (portion of a
process)
Maria Hybinette, UGA^8
Virtual Memory Intuition
! Idea: OS keeps unreferenced pages on disk
» Slower, cheaper backing store than memory
! Process can run when not all pages are loaded into
main memory
! OS and hardware cooperate to provide illusion of large
disk as fast as main memory
» Same behavior as if all of address space in main memory » Hopefully have similar performance
! Requirements:
» OS must have mechanism to identify location of each page in address space in memory or on disk » OS must have policy for determining which pages live in memory and which on disk Maria Hybinette, UGA^9
Virtual Address Space
Mechanisms
! Each page in virtual address space maps to one of three
locations:
» Physical main memory: Small, fast, expensive » Disk (backing store): Large, slow, cheap » Nothing (error): Free Disk Storage main memory cache registers Smaller, faster and more expensive Bigger, smaller and cheaper Leverage memory hierarchy of machine architecture Each layer acts as “backing store” for the layer above Maria Hybinette, UGA^10
Virtual Address Space
Mechanisms
! Extend page tables with an extra bit to
indicate whether it is in memory
(resident bit): valid (invalid) or on
disk.
» permissions (r/w), valid » Page in memory: valid bit set in page table entry (PTE) » Page out to disk: valid bit cleared ( invalid )
- PTE points to block on disk
- Causes trap into OS when page is referenced
- Trap: page fault (^11) (^11) 0 (^00) M Frame # valid-invalid bit page table Maria Hybinette, UGA^11
Virtual Memory Mechanisms
! Hardware and OS cooperate to translate addresses
! First, hardware checks TLB for virtual address
» TLB hit: Address translation is done; page in physical memory » TLB miss:
- Hardware or OS walk page tables
- If PTE designates page is valid, then page in physical memory
! Not in main memory: Page fault (i.e., invalid )
» Trap into OS (not handled by hardware) » OS selects victim page in memory to replace
- Write victim page out to disk if modified (add dirty bit to PTE) » OS reads referenced page from disk into memory » Page table is updated, valid bit is set » Process continues execution PTE in TLB? CPU checks TLB PTE in TLB? Access page table OS Instructs CPU to read the page from disk Page in MM? physical address^ CPU generates CPU activates I/O hardware Update TLB Page transferred from disk to main memory Memory Full? Page replacement Page tables updated Yes Yes Yes No No No Page fault routine
Paging Operations
Maria Hybinette, UGA^19
Page Replacement Continued
! FIFO: Replace page that has been in memory the
longest
» Intuition: First referenced long time ago, done with it now » Advantages:
- Fair: All pages receive equal residency
- Easy to implement (circular buffer) » Disadvantage: Some pages may always be needed
! LRU: Replace page not used for longest time in past
» Intuition: Use past to predict the future » Advantages:
- With locality, LRU approximates OPT » Disadvantages:
- Harder to implement, must track which pages have been accessed
- Does not handle all workloads well Maria Hybinette, UGA^20
Evaluate Page Replacement
Algorithms
! Want lowest page-fault rate.
! Evaluate algorithm by running it on a particular
string of memory references (reference string)
and computing the number of page faults on
that string.
! Convert address to page
» Example: Assume 100 bytes per page and
- Assume the address sequence: ! 0100, 0210, 0250, 0300, 0350, 0380, 0400, 0160, 0250, 0505, 0100, 0110, 0230, 0350, 0450, 0450, 0500, 0500
- Convert address to a reference string: ! 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5. Maria Hybinette, UGA^21
Example: FIFO Page
Replacement
! FIFO: Replace page that has been in memory the
longest
Maria Hybinette, UGA^22
Page Replacement Example
OPT FIFO LRU
ABC
B D A D B C B
A
Page reference string: ABCABDADBCB Three pages of physical memory
Page Replacement: Add
memory
! Add more physical memory, what happens to
performance?
» Ideally the numbers of page faults should should
decrease as number of available frames increases
» If 1 page frame : Number of page faults?
- 12 page faults, one fault for every page (11 faults)
» If 12 frames : Number of page faults?
First-In-First-Out (FIFO)
Algorithm: Add Memory
! 4 frames
1 2 3 4 1 2 5 3 4
! Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
! 3 frames (3 pages can be in memory at a time per process)
1 2 3 4 5 1 2 3 4 5 ! FIFO Replacement – Belady’s Anomaly » more frames! less page faults
Maria Hybinette, UGA^25
Page Replacement Comparison
! Add more physical memory, what happens to
performance?
» LRU, OPT: Add more memory, guaranteed to have
fewer (or same number of) page faults
- Smaller memory sizes are guaranteed to contain
a subset of larger memory sizes
» FIFO: Add more memory, usually have fewer page
faults
- Belady’s anomaly: May actually have more page faults! Maria Hybinette, UGA^26
Implementing LRU
! Software Perfect LRU
» OS maintains ordered list of physical pages by reference time » When page is referenced: Move page to front of list (top) » When need victim: Pick page at back of list (bottom) » Trade-off: Slow on memory reference, fast on replacement
! Hardware Perfect LRU
» Associate register with each page » When page is referenced: Store system clock in register » When need victim: Scan through registers to find oldest clock » Trade-off: Fast on memory reference, slow on replacement (especially as size of memory grows)
! In practice, do not implement Perfect LRU
» LRU is an approximation anyway, so approximate more » Goal: Find an old page, but not necessarily the very oldest Maria Hybinette, UGA^27
Clock or Second Chance
Algorithm
! Hardware
» Keep use (or reference ) bit for each page frame initialized to 0. » When page is referenced: set use bit ( 1 )
! Operating System
» Page replacement: Look for page with use bit cleared ( 0 ) (has not been referenced for awhile) » Implementation:
- Keep pointer to last examined page frame
- Traverse pages in circular buffer
- Clear use bits while searching for replacement
- Stop when find page with already cleared use bit, replace this page Maria Hybinette, UGA^28
Clock Algorithm Example
! Worst Case:
» All bits are set -> FIFO (slow)
Clock Extensions
! Replace multiple pages at once
» Intuition: Expensive to run replacement algorithm and to write single block to disk » Find multiple victims each time
! Two-handed clock
» Intuition:
- If takes long time for clock hand to sweep through pages, then all use bits might be set
- Traditional clock cannot differentiate between usage of different pages » Allow smaller time between clearing use bit and testing
- First hand: Clears use bit
- Second hand: Looks for victim page with use bit still cleared
More Clock Extensions
! Add software byte
» Intuition: Keep track of history when last used
! Implementation: Reference bit
» With each page associate a bit, initially = 0
» When page is referenced bit set to 1.
» Keep a history of reference bit in an 8 bit byte:
- Shift reference bit for each page to high order bit, and other bits right one bit.
- 11000100 (more recently used than below)
- 01110111
Maria Hybinette, UGA^37
Questions
! How to allocate memory across competing
processes?
! What is thrashing? What is a working set?
! How to ensure working set of all processes
fit?
Maria Hybinette, UGA^38
Allocating Memory across
Processes
! Problem:
» 2 processes and 25 free frames how are they divided up?
! Three General Approaches:
» Global Replacement
» Per-Process Replacement
» Per-User Replacement
Maria Hybinette, UGA^39
Global Replacement
! Global replacement
» Pages from all processes lumped into single replacement pool
- Example: Run clock over all page frames » Each process competes with other processes for frames » Advantages:
- Flexibility of allocation
- Minimize total number of page faults » Disadvantages
- One memory-intensive process can hog memory, hurt all processes
- Paging behavior of one process depends on the behavior of other processes Maria Hybinette, UGA^40
Per-process replacement
! Per-process free pool of pages
» Equal, Fixed Allocation: Fixed number of pages per process
- 100 frames and 5 processes, give each 20 pages.
- Fixed fraction of physical memory » Proportional Allocation:
- Proportional to size of address space
- Adjust size allocated if a process have higher priority
! Page fault in one process only replaces frame of that
process
! Advantage: Relieves interference from other processes
! Disadvantage: Potentially inefficient allocation of
resources
Per-User Replacement
! Advantages: Users running more processes
cannot hog memory
! Disadvantage: Inefficient allocation
Over Committing Memory
! When does the Virtual Memory illusion break?
! Example:
» Set of processes frequently referencing 33 important pages » Physical memory can fit 32 pages
! What happens?
» System Repeat Cycle:
- Reference page not in memory
- Replace a page in memory with newly referenced page
- Replace another page right away again, since all its pages are in active use…
Maria Hybinette, UGA^43
Thrashing
! Thrashing:
» Spends more time paging than execution, i.e. system reading and writing pages instead of executing useful instructions » Average memory access time equals to disk access time » Illusion breaks: Memory appears slow as disk rather than disk appearing fast as memory
! Add more processes, thrashing gets worse
! System is reading and writing pages instead of
executing useful instructions
» Implication: Average memory access time = disk access time » Memory appears as slow as disk, instead of disk appearing as fast as memory Maria Hybinette, UGA^44
System does not know it is
thrashing
! If a process does not have “enough” pages, the page-fault rate is very high. This leads to: » low CPU utilization. » operating system thinks that it needs to increase the degree of multiprogramming. » another process added to the system ! Why the CPU utilization decreases: » Suppose a process need more frames, starts faulting, removing frames from others, in turn making the other processes fault » Processes queue up for the paging device, CPU decreases » OS add processes that immediately need new frames further taking away pages from running processes Maria Hybinette, UGA^45
Thrashing: Solutions
! Limit thrashing by using a local replacement
» Process does not steal frames from other and cause latter to thrash » Average service time for a page fault will still increase…
! Admission Control:
» Determine of much memory each process needs » Long-term scheduling policy:
- Run only processes whose memory requirement can be satisfied
! What if memory requirement of one process is too
high?
» Observation: a process moves through different ``localities’’ through out is lifetime
- Locality: Set of pages that are actively used together » Solution: Amortize page allocated so that a process get enough page for its current locality Maria Hybinette, UGA^46
Motivation for Solution
! Thrashing cannot be fixed with better replacement
policies
» Page replacement policies do not indicate that a page must be kept in memory » Only show which pages are better than others to replace
! Student’s analogy to thrashing: Too many courses
» Solution: Drop a course
! OS solution: Admission control
» Determine how much memory each process needs » Long-term scheduling policy
- Run only those processes whose memory requirements can be satisfied » What if memory needs of one process are too large?
Working Set
! Informal definition
» Collection of pages the process is referencing frequently » Collection of pages that must be resident to avoid thrashing
! Formal definition
» Assume locality; use recent past to predict future » Pages referenced by process in last T seconds of execution » Working set changes slowly over time
! Example:
A A B C B B B C D C D E B B E E D F B F D B B E D B
A B C B D E F
" = 8^ Time
Balance Set
! Motivation: Process should not be scheduled unless
working set is resident in main memory
! Divide runnable processes into two groups:
» Active: Working set is loaded » Inactive: Working set is swapped to disk
! Balance set: Sum of working sets of all active
processes
! Interaction with scheduler
» If balance set exceeds size of memory, move some process to inactive set
- Which process??? » If balance set is less than size of memory, move some process to active set
- Which process? » Any other decisions?
Memory Hierarchy
Disk Storage main memory cache registers Smaller, faster and more expensive Bigger, smaller and cheaper Leverage memory hierarchy of machine architecture Each layer acts as “backing store” for the layer above
Average Access Time
calculation
! Average access time calculation:
» H : Percentage of references that hit page in physical memory » CAccessMemory : Cost of referencing page in memory (e.g., 100 ns) » CPageFault : Cost of page fault (e.g., 20 ms or 20,000,000ns) » H * CAccessMemory + (1-H) * CPageFault
! Example: 1 out of every 33 references misses, H = 97%
» 0.97 * (100 ns) + (0.03) * (20000000ns) = 750000 ns = 750 us » More than 1000 times slower than physical memory access
! Need very high hit rate for acceptable performance
