VLSI Assignment # 01
COMSATS University Islamabad, Abbottabad Campus
Department of Electrical & Computer Eng
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Submitting to:
Proof. Dr. Imran Shehzad sb
BS Electrical and Electronics Engineering
Date: 28 Apr 2023
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VLSI Assignment # 01, Assignments of Very large scale integration (VLSI)
An assignment for a VLSI course at COMSATS University Islamabad, Abbottabad Campus. It explains the layout design rules and lambda design rules with examples. It also describes the steps involved in the fabrication process of a CMOS transistor.
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VLSI Assignment # 01
COMSATS University Islamabad, Abbottabad Campus
Department of Electrical & Computer Engineering
Submitting to:
Proof. Dr. Imran Shehzad sb
BS Electrical and Electronics Engineering
Date: 28 Apr 2023
name
roll no
Question 1: what do you know about layout design rules? Explain lambda design rules
with few examples.
Answer: layout design rule is the set of rules that must be followed in designing a layout. It
acts as an interface between circuit designer and process engineer during the manufacturing phase. It ensures that the patterns on the processed wafers will preserve the topology and geometry of the designs. It also gives us the dimension and spacing constrains between objects on the same or different layers.
Lambda design Rule:
All rules are defined in terms of single parameter called lambda(λ) design rule. These rules are chosen so that a design can easily be ported over a series of fabrication processes, as technology scales with time for deep submicron designs, some companies use absolute design rules as scaling does not always work. Basic rules: the follow should be kept in mind e.g., minimum layer size/width, minimum layer separation and minimum layer overlap. (1) Rules for N-well. Minimum width = 10λ. Wells at same potential with spacing = 6λ. Wells at same potential = 0λ. (2) Rules for Active area. Minimum width = 3λ. Minimum spacing = 3λ. Source/Drain active to well edge = 5λ. Substrate/well contact active to well edge = 3λ.
- Rules for poly. Minimum width = 2λ Minimum spacing = 2λ Minimum gate extension of active = 2λ Minimum field poly to active = 1λ
Step 1: First we choose a substrate as a base for fabrication. For N- well, a P-type silicon substrate is selected. Step 2 – Oxidation: The selective diffusion of n-type impurities is accomplished using SiO as a barrier which protects portions of the wafer against contamination of the substrate. SiO 2 is laid out by oxidation process done exposing the substrate to high-quality oxygen and hydrogen in an oxidation chamber at approximately 1000^0 c. Step 3 – Growing of Photoresist: At this stage to permit the selective etching, the SiO layer is subjected to the photolithography process. In this process, the wafer is coated with a uniform film of a photosensitive emulsion. Step 4 – Masking: This step is the continuation of the photolithography process. In this step, a desired pattern of openness is made using a stencil. This stencil is used as a mask over the photoresist. The substrate is now exposed to UV rays the photoresist present under the exposed regions of mask gets polymerized. Step 5 – Removal of Unexposed Photoresist: The mask is removed, and the unexposed region of photoresist is dissolved by developing wafer using a chemical such as Trichloroethylene.
Step 6 – Etching: The wafer is immersed in an etching solution of hydrofluoric acid, which removes the oxide from the areas through which dopants are to be diffused. Step 7 – Removal of Whole Photoresist Layer: During the etching process , those portions of SiO2 which are protected by the photoresist layer are not affected. The photoresist mask is now stripped off with a chemical solvent (hot H2SO4). Step 8 – Formation of N-well: The n-type impurities are diffused into the p-type substrate through the exposed region thus forming an N- well. Step 9 – Removal of SiO2: The layer of SiO2 is now removed by using hydrofluoric acid.
Using diffusion process three n+ regions are developed for the formation of terminals of NMOS. Step 14 – Removal of Oxide: The oxide layer is stripped off. Step 15 – P-type Diffusion: Similar to the n-type diffusion for forming the terminals of PMOS p-type diffusion are carried out. Step 16 – Laying of Thick Field oxide: Before forming the metal terminals a thick field oxide is laid out to form a protective layer for the regions of the wafer where no terminals are required. Step 17 – Metallization: This step is used for the formation of metal terminals which can provide interconnections. Aluminium is spread on the whole wafer.
Step 18 – Removal of Excess Metal: The excess metal is removed from the wafer. Step 19 – Formation of Terminals: In the gaps formed after removal of excess metal terminals are formed for the interconnections. Step 20 – Assigning the Terminal Names: Names are assigned to the terminals of NMOS and PMOS transistors.