RAKESH ASERY(09EC73)
CE Amplifier design on Multisim
Figure: CE Amplifier with voltage divider biasing
Figure: Response of CE amplifier
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VLSI software Laboratory, Lab Reports of Engineering
CE Amplifier design, Buffer Amplifier design, NMOS Amplifier design, Wein bridge generator design, Square wave generator design, RC phase oscillator design, JFET design, Astable Multivibrator design, Mono-stable Multi-vibrator Design, Introductuion to Xilinx ISE 7.1i software, Design Full Adder, Design Half adder, Design half substractor, Design AND Gate, Design NOR Gate, Design XNOR Gate, Design NAND Gate, Design OR Gate, Design XOR Gate, Design fullsubtractor, Design 4to1Multiplexer, Design 8
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2013/2014
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CE Amplifier design on Multisim Figure: CE Amplifier with voltage divider biasing Figure: Response of CE amplifier
OBJECT:- Introductuion to Xilinx ISE 7.1i software. XILINX SOFTWARE The Xilinx ISE 7.1i software will be used in this text. All menus structures and screen shots are taken from the ISE 7.2i version. The Integrated Software Environment (ISE™) is the Xilinx® design software suite that allows you to take your design from design entry through Xilinx device programming. The ISE Project Navigator manages and processes your design through the following steps in the ISE design flow. VHDL Design Entry The Xilinx ISE tools allow the design to be entered several ways including graphical schematics, state machine diagrams, VHDL, and Verilog.This tutorial will focus on VHDL entry, but the other methods are similar and can be easily explored once the reader is comfortable with theISE software. Starting a project Start the Xilinx ISE Project Navigator. Choose File ) New Project.A popup dialog box will appear. Enter tutor1 for Project Name. Forthe Project Location, select the directory where the project will be stored (i.e., Z:nXProjntutor1) for your project. Figure 1: The New Project dialog box is used to enter the project and FPGA deviceinformation required to create a new project.
Creating a design
Choose Project ) New Source.... A popup dialog box will appear.Select VHDL Module from the list on the left and enter top levelfor the File Name. Make sure the Add to Project option is checkedand click Next.
Figure 3: Enter the input and output signals for the new VHDL module inthe VHDL Source Definition dialog box. Module View window will open up that ¯le in the main window. The Process View window is displayed in the lower left-hand side.This window provides access to the pin assignment ¯le, simulator, compiler settings, compilation reports, compiler controls, and FPGA programmer. Click on the + sign beside each item in the Process Viewwindow to view the di®erent options available.Finally, the bottom pane is the Console window. All text outputfrom the Project Navigator, including warning and error messages, aredisplayed here. Writing the VHDL model Look at the top level.vhd VHDL file that you generated earlier. Thefirst four lines of code indicate which VHDL libraries and packages are needed for this VHDL module. IEEE.STD LOGIC 1164, Next, you will ¯nd the Architecture statement. This is the sectionwhere the behavior or functionality of this VHDL module is defined.Enter led1 <= NOT pb; on a line between begin and end Behavioral;. This line of VHDL code indicates that an inverter is to be placed between the input pb and the output led1. Choose file Save to save these changes.
Figure 4: The Xilinx Project Navigator is the heart of the Xilinx ISE software. Figure 5: The completed VHDL code for the example project Checking the VHDL syntax Make sure the top level.vhd item in the Module View window is highlighted. If it is not, then single click on it to make it active. In the Process View window,
device. When programming is finished, Programming Succeeded should appear in the main window. Figure 6: The completed VHDL code for the toggle °ip-°op example. RESULT:- I have successfully study introductuion to Xilinx ISE 7.1i software.
OBJECT:-Design Full Adder using appropriate software like VHDL (xilinx). Full Adder CODING :- entity RAFADDER is Port ( A : in std_logic; B : in std_logic; C : in std_logic; SUM : out std_logic; CARRY : out std_logic); end RAFADDER; architecture Behavioral of RAFADDER is begin SUM <= A XOR B XOR C; CARRY <= (A AND B) OR (B AND C) OR (C AND A); end Behavioral; SCHEMETIC DIAGRAM OF SUM :-
OBJECT:-Design Half adder using appropriate software like VHDL (xilinx). Half adder CODING :- entity RAHADDER is Port ( A : in std_logic; B : in std_logic; SUM : out std_logic; CARRY : out std_logic); end RAHADDER; architecture Behavioral of RAHADDER is begin SUM <= A XOR B ; CARRY <= A AND B ; end Behavioral; SCHEMETIC DIAGRAM OF SUM :- TRUTH TABLE :-
SCHEMATIC DIAGRAMOF CARRY:-
TRUTH TABLE :-
RESULT:- We have successfully design Half adder.
TRUTH TABLE :-
SCHEMATIC DIAGRAM OF BORROW :-
TRUTH TABLE :-
RESULT:- We have successfully design half substractor.
OBJECT :-Design AND Gate using appropriate software like VHDL (xilinx).
AND Gate CODING :-
entity AND is Port ( a : in std_logic; b : in std_logic; c : out std_logic); end AND; architecture Behavioral of AND is begin c <= a AND b ; end Behavioral; SCHEMATIC DIAGRAM :- TRUTH TABLE :- RESULT:- We have successfully design AND Gate.
OBJECT :-Design XNOR Gate using appropriate software like VHDL (xilinx). XNOR Gate CODING :- entity RAXNOR is Port ( A : in std_logic; B : in std_logic; C : out std_logic); end RAXNOR; architecture Behavioral of RAXNOR is begin C <= A XNOR B ; end Behavioral; SCHEMATIC DIAGRAM :- TRUTH TABLE :- RESULT:- We have successfully design XNOR Gate.
OBJECT :-Design NAND Gate using appropriate software like VHDL (xilinx). NAND Gate CODING :- entity RANAND is Port ( A : in std_logic; B : in std_logic; C : out std_logic); end RANAND; architecture Behavioral of RANAND is begin C <= A NAND B ; end Behavioral; SCHEMATIC DIAGRAM :- TRUTH TABLE:- RESULT:- We have successfully design NAND Gate.