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System
architecture The CPU
1.1 Systems Architecture
Fetch, decode & execute cycle
- Identify the function of the fetch, decode & execute cycle
- Explain the role and tasks performed at each stage of the cycle
- Identify what CPU components are involved at each stage
Unit 1 Systems architecture, memory and storage Fetch – Decode – Execute
- The CPU operates by repeating three operations: - FETCH – causes the next instruction and any data involved to be fetched from main memory - DECODE – decodes the instruction - EXECUTE – carries out the instruction
- Repeat…
Unit 1 Systems architecture, memory and storage Fetch
- Fetch the data and instructions (program) from main memory and then store in it’s own internal memory areas.
- Memory areas are called registers
- The information is carried in a hardware path called the address bus
- The CPU places the address of next item to be fetched on to the address bus
- Data from this address moves from main memory to CPU by travelling along an hardware path known as data bus The ‘Program Counter’ copies the address of the next instruction it contains into the ‘ Memory Address Register ’ (MAR). The ‘ Memory Address Register ’ places the address to be used on to the ‘ Address Bus’ The ‘ Memory Address Register ’ triggers a ‘read’ signal This causes main memory (RAM) to place the instruction being asked for on to the ‘ Data Bus ’ The instruction from the data bus is loaded into the ‘ Memory Data Register ’ The ‘Memory Data Register ’ copies the instruction into the ‘ Instruction Register ’. The memory data register is used whenever anything is to go from the CPU to main memory. So the next instruction will be copied from the memory to the MDR and then into the CIR
Unit 1 Systems architecture, memory and storage Decode
- CPU needs to make sense of the instructions
- The CPU will be designed to understand a certain set of instructions. These are called the Instruction set
- The CPU decodes the instructions and prepares the various areas within the chip in readiness for the next step
The CPU examines the
instruction in the ‘ Current
Instruction Register ’ (CIR)
The CPU decodes’ the data.
Unit 1 Systems architecture, memory and storage
Class Example:
Add 8 + 4
Roles to perform:
- Program Counter (PC)
- Current Instruction Register (CIR)
- Memory Address Register (MAR)
- Memory Data Register (MDR)
- Accumulator
You will need:
- Copies of the Instructions
- Copies of the data in location 10
- Memory location 10
- Memory location 11
- Copy of the number 4
- A card to output the result
Unit 1 Systems architecture, memory and storage Example – Step 1 (Add 8 + 4)
- PC points to next instruction in location 5
- Instruction is passed to the CIR and PC is incremented
- Memory location 10 is passed to the MAR
- The value in location 10 is passed from main memory to the MDR
- 8 is loaded into the accumulator
5 LDA 10
6 ADD
7 STO 11
Program Counter
Unit 1 Systems architecture, memory and storage Example – Step 3
- PC points to the next instruction in location 7
- Instruction is passed to the CIR
- Memory location 11 is passed to the MAR
- Total value 12 transferred from the accumulator into memory location 11
5 LDA 10
6 ADD
7 STO 11
Program Counter
Unit 1 Systems architecture, memory and storage Your task:
- Take each register and explain its role within the fetch, decode & execute cycle
