CS 61C Spring 2014 Discussion 5 – Direct Mapped Caches
In the following diagram, each block represents 8 bits (1 byte) of data. Our memory is byte-addressed,
meaning that there is one address for each byte. Compare this to word-addressed, which means that
there is one address for each word.
The Geometry of Caches
Main
Memory
...
6
5
4
3
2
1
0
Cache
Number
Main
Memory
03210
7654
111 10 9 8
15 14 13 12
219 18 17 16
23 22 21 20
327 26 25 24
31 30 29 28
CPU
Cache
Index
Number
Offset
3 2 1 0
0
1
Tag bits Index bits Offset bits Total
29 1 2 32
1 word=4 bytes =32bits
Index bits=log2(Number of index rows )
Offset bits=log2(Number of offsets columns)
1. Direct mapped caches
1. How many bytes of data can our cache hold? 8 bytes How many words? 2 words
2. Fill in the “Tag bits, Index bits, Offset bits” with the correct T:I:O breakdown according to the
diagram.
3. Let’s say we have a 8192KiB cache with an 128B block size, what is the tag, index, and offset
of 0xFEEDF00D?
FE ED F0 0D
1111 1110 1110 1101 1111 0000 0000 1101
Tag : 1 1111 1101 (0x1FD) Index: 1101 1011 1110 0000 (0xDBE0) Offset: 000 1101 (0x0D)
4. Fill in the table below. Assume we have a write-through cache, so the number of bits per row
includes only the cache data, the tag, and the valid bit.
Address size
(bits) Cache size Block size Tag bits Index bits Offset bits Bits per row
16 4KiB 4B 4 10 2 37
32 32KiB 16B 17 11 4 146
32 64KiB 16B 16 12 4 145
64 2048KiB 128B 43 14 71068
Fall 2014 –
