1489 Quad Line Receiver - Microcontroller Applications | ECE 4510, Study notes of Microcomputers

Material Type: Notes; Professor: Grantner; Class: Microcontroller Applications; Subject: Electrical & Computer Engineer; University: Western Michigan University; Term: Fall 2009;

Typology: Study notes

Pre 2010

Uploaded on 08/17/2009

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ao RS 232C Une receive (Motorola) tysa FIGURE 9.17 The 1449 line receiver FUNCTIONAL DESCRIPTION The 1489 and 1489A are quad fine receivers whose electrical characteristics conform to EIA specification RS-232C. Each receiver has a single data input that can eccept signal swings of up to +30 V. The output of each receiver is TTL/DTL compatible, and includes a 2kO resistor pull-up to V,.. An internal feedback resistor causes the input to exhibit hysteresis so that a.c. noise immunity is maintained st s high level even near the switching threshold. For both devices, when : driver . in s LOW state on the output, the input may drop as LOW as 1,25 |. Both devices are guaranteed to switch to the HIGH state when the input voltage is below 0.75 V. Once the output has switched to the HIGH state, the input rise to T.0V for the or 1.75 V for the a change in the output, The is guaranteed to it when its input reaches 1. 2 1489A is quaranteed itch to a LOW output when its in, . Because of the hysteresis in switching thresholds, the devices can receive signals with superimposed noise or with slow rise and fall times without generating oscillations . ‘on the output. The hold levels may be offset by a constant voltage LOGIC SYMBOL INA ah ouT ACA we —4 § sour rca 3 INC ae OUT RCC 2.S.e. bies to the response contral it. A capacitor added to the response co! Voc = pin 14 ofthe recelva or applications nthe ce = B ie3. The companion line driver is tl : gnd = pin? CIRCUIT DIAGRAM (one receiver) Wee Output Response control Input 0 CONNECTION DIAGRAM ' Top view AIN GT 140) Veo ARC. [2 13] DIN A OUT [3 120 DRC. BIN(4 11) DOUT BR.C. is 100 CIN BOUT 16 $f CR.c, gnd 17 8) C OUT