18-447
Computer Architecture
Final Review Session
Prof. Onur Mutlu
Carnegie Mellon University
Spring 2015, 5/1/2015
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Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
18-447 Computer Architecture Final Review Session, Slides of Network Technologies and TCP/IP
Carnegie Mellon University. Spring 2015, 5/1/2015 ... Cycle-level modeling of the MESI cache coherence protocol ... Three cheat sheets allowed.
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Computer Architecture
Final Review Session
Prof. Onur Mutlu Carnegie Mellon University Spring 2015 , 5 / 1 / 2015
Lab 6 Extra Credit
2.5% Ashish Shrestha (ashresth) 2.5% Amanda Marano (amarano) 2.5% Pete Ehrett (wpe) 2.0% Jared Choi (jaewonch) 2.0% Akshai Subramanian (avsubram) 2.0% Sohil Shah (sohils) 2.0% Raghav Gupta (raghavg) 1.5% Kais Kudrolli (kkudroll)
Extra Credit for Course Evaluations
0.25% extra credit for everyone in the class if more than 90 % (i.e., 25 ) of you fill out the evaluations
Extra Credit Lab 8 : Multi-Core Cache Coherence
Completely extra credit (all get 5 % for free; can get 5 % more) Last submission accepted on May 10 , 11:59pm; no late submissions Cycle-level modeling of the MESI cache coherence protocol
Course Grades So Far
0 1 2 3 4 5 6 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 Number of Students Bins (percentage) AVG = 57 Median = 58 STDDEV = 6. Max = 66 Min = 43 Max_possible = 71 Max_possible + EC = 87.
A Note on 740 , Research, Jobs/Internships I am teaching 740 next semester (Fall 2015 ) Lectures M, W 7:30-9:20pm Recitations T 7:30-9:20pm If you are enjoying 447 and are doing well, you can take it feel free to talk with me If you are excited about Computer Architecture research or looking for a job/internship in this area talk with me
Lecture Schedule (Second Half)
The memory hierarchy Caches, caches, more caches Virtualizing the memory hierarchy: Virtual Memory Main memory: DRAM Main memory control, scheduling Memory latency tolerance techniques Non-volatile memory Multiprocessors Coherence and consistency In-memory computation and predictable performance Multi-core issues (e.g., heterogeneous multi-core) Interconnection networks
Lecture Schedule (First Half)
Fundamentals, ISA, ISA Tradeoffs Single-cycle Microarchitectures Multi-cycle and Microprogrammed Microarchitectures Pipelining Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … Out-of-Order Execution Issues in OoO Execution: Load-Store Handling, … Alternative Approaches to Instruction Level Parallelism