18-447: Computer Architecture Lecture 18: Virtual Memory III, Summaries of Computer Architecture and Organization

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18-447: Computer Architecture

Lecture 18: Virtual Memory III

Yoongu Kim

Carnegie Mellon University

Spring 2013, 3/

Upcoming Schedule

• Today: Lab 3 Due
• Today: Lecture/Recitation
• Monday (3/4): Lecture – Q&A Session
• Wednesday (3/6): Midterm 1
  • 12:30 – 2:
  • Closed book
  • One letter-sized cheat sheet
    • Can be double-sided
    • Can be either typed or written

Review of Last Lecture

• Two approaches to virtual memory

1. Segmentation

• Not as popular today

2. Paging

• What is usually meant today by “virtual memory”
• Virtual memory requires HW+SW support
• HW component is called the MMU
• Memory management unit
• How to translate : virtual ↔ physical addresses?

Review of Last Lecture (cont’d)

1. Segmentation

• Divide the address space into segments
  • Physical Address = BASE + Virtual Address
• Case studies: Intel 8086, 80286, x86, x86-
• Advantages
  • Modularity/Isolation/Protection
  • Translation is simple
• Disadvantages
  • Complicated management
  • Fragmentation
  • Only a few segments are addressable at the same time

Today’s Lecture

• More on Paging

1. Translation

2. Protection

3. TLB Management

4. Page Faults

5. Page Size

6. Software Side

1. TRANSLATION

PDE 0 NULL

Translation: Two-Level Page Table

pte_t *PAGE_DIRECTORY[1<<10];

PAGE_DIRECTORY[0]=malloc((1<<10)*sizeof(pte_t));

PAGE_DIRECTORY[0][7]=2;

PDE 0^ &PT 0

PDE 1^ NULL

PDE 1023^ NULL

31 0

PAGE_DIR

NULL PTE 0

PTE 7

NULL PTE 1023

19 0

NULL

PAGE_TABLE 0

000000010 PTE 7

VPN[19:0]=0000000000_

Directory index Table index

Two-Level Page Table (x86)

• CR3 : Control Register 3 (or Page Directory Base Register )
  • Stores the physical address of the page directory
  • Q: Why not the virtual address?

Multi-Level Page Table (x86-64)

• Q: Why so many levels?
• A: Virtual address space is extremely large; too many empty PDEs. Need to unallocate them.

Translation: Segmentation + Paging

x86: Privilege Level (Review)

• Four privilege levels in x86 (referred to as rings )
  • Ring 0: Highest privilege (operating system)
  • Ring 1: Not widely used
  • Ring 2: Not widely used
  • Ring 3: Lowest privilege (user applications)
• Current Privilege Level (CPL) determined by:
  • Address of the instruction that you are executing
  • Specifically, the Descriptor Privilege Level (DPL) of the code segment

“Supervisor”

“User”

x86: A Closer Look at the PDE/PTE

• PDE: Page Directory Entry (32 bits)
• PTE: Page Table Entry (32 bits)

PTE PPN Flags

PDE &PT Flags

Protection: PTE’s Flags

• Protects one page at a time

Protection: PDE + PTE = ???