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CS/COE 1541 Computer Architecture - Spring 2002
Exam
Directions : This exam is closed book—put all books and notes under your desk on the floor. There are five questions with several subquestions. All questions are marked with their point values. There should be plenty of workspace provided in the exam booklet, but if you need extra pages, you may use a blank piece of paper.
Be sure to show all work and turn in any extra pages that you use. If you do not show your work or your work is illegible, you will not receive any partial credit for a wrong answer.
All questions are weighted the same—20 points each. The point value for each subquestion is indi- cated.
Write your name on each exam page!
Topics covered by each question:
Question 1 - CPU performance with caches Question 2 - Processor caches Question 3 - Virtual memory Question 4 - Memory organization Question 5 - Quick answer
Question 1 - CPU performance with caches
For the following questions, consider a program in which 20% of the instructions are memory load or store instructions. Assume that there is a main memory access time of 50 n.sec., a 500 MHz pro- cessor clock rate, and a CPI of 2 for a machine with a perfect cache (i.e., the data and instructions are always found in the first level cache).
(a) 10 points. Consider a machine with an instruction cache miss rate of 3% and a data cache miss rate of 10%. What is the effective CPI of this machine?
(b) 10 points. Assume that we have two cache hierarchies: one in machine 1 and one in machine 2.
- Machine 1: 64 KB level-one data cache with a 10 n.sec. access time and a miss rate of 10%
- Machine 2: 8 KB level-one data cache with a 2 n.sec. access time and a miss rate of 17%, and a 1 MB level-two cache with a 16 n.sec. access time and a miss rate of 27%.
Assuming that the I-cache miss rate is 0%, what is the effective CPI of machine 1 and 2? Which machine has better performance?
Question 3 - Virtual memory
A virtual memory system has a page size of 4,096 bytes, eight virtual pages, four physical pages, and uses the LRU page replacement policy (with a reference bit). Suppose that we have the page table (all fields in the page table are shown in binary notation):
(a) How many bits are there in a virtual address for this memory system?
(b) Suppose a page fault occurs on virtual page 6. Which physical page will be replaced?
(c) What is the main memory address for virtual address 5F38(hex)?
Suppose we add a two entry, fully associative TLB to the virtual memory system above. The TLB uses the LRU replacement policy to select a TLB entry to replace on a miss. The contents of the TLB are (all fields in the TLB are shown in binary notation):
(d) Using the page table above and the TLB, what are the contents of the TLB after the references: a Write to address 113F(hex) and a Read to address 4F0A(hex).
You can write your answer in the table below:
Entry Valid Reference Dirty Physical Page 0 0 0 0 -- 1 1 1 0 11 2 0 0 0 -- 3 0 0 0 -- 4 1 1 0 01 5 1 0 1 10 6 0 0 0 -- 7 1 1 1 00
Entry Valid Reference Dirty Virtual Page Physical Page 0 0 0 0 -- -- 1 1 1 0 001 11
Entry Valid Reference Dirty Virtual Page Physical Page 0 1
Question 4 - Memory organization
(a) 6 points. For DRAM memory cells, answer the following questions:
- Why must DRAM be refreshed?
- What steps are done to read a DRAM cell?
(b) 14 points. Draw all connections and components needed to build a 16x16 memory module using 8x8 memory chips.
Blank page for work space
