CPE/EE 422/522 SP2004, Lab Assignment 4
4-bit Signed Binary Number (2 s complement)
Multiplier
(Undergraduate 100 points -- Graduate 80 points)
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The purpose of this laboratory project is to give each student the opportunity to develop a
practical logic design using both schematic capture and/or VHDL that will implement a 4-bit
multiplier for signed binary number using Booth s algorithm. The design will take two 4-bit
singed binary numbers (2 s complement) from Altera UP 1 Educational Trainer’s FLEX_SW1
switches and display the product in decimal format as well as the sign on two of the Altera UP 1
Educational Trainer’s seven-segment LEDs.
Background
Problem 4.15 (pages 158-159) of the textbook has a detailed description of the Booth s algorithm.
You can try this nice on-line Booth s algorithm simulator also:
(http://www.ecs.umass.edu/ece/koren/arith/simulator/Booth/)
Pin Assignment
Altera Pin Numbers for FLEX_PB1 push button
FLEX_PB1 push button connects to pin 28 of the EPF10K20 FPGA device
Altera Pin Numbers for Crystal Oscillator
The Altera UP 1 Educational Trainer’s board contains a 25.175-MHz crystal oscillator. The
output of the oscillator drives a global clock input on the EPF10K20 FPGA device (Pin91).
Altera Pin Numbers for the FLEX_SW1 switches connections
FLEX_SW1 Pin Assignment
Switch EPF10K20 Pin
FLEX_SW1-1 41
FLEX_SW1-2 40
FLEX_SW1-3 39
FLEX_SW1-4 38
FLEX_SW1-5 36
FLEX_SW1-6 35
FLEX_SW1-7 34
FLEX_SW1-8 33
