ECE 349 Homework Assignment #7 Solutions: Digital Logic Circuits - Prof. James F. Frenzel, Assignments of Electrical and Electronics Engineering

The solutions to homework assignment #7 of ece 349, a digital logic circuits course. Students are required to solve problems 13.3, 13.5, 13.6, and 13.9, which involve boolean algebra and k-maps. The solutions include step-by-step calculations and the final results.

Typology: Assignments

Pre 2010

Uploaded on 08/19/2009

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ECE 349 Homework Assignment #7 Solutions
Show your work! You will not receive full credit for the answer alone.
1. Do problem 13.3 on page 350 of your text.
(a) A+=A(B0+X) + A0(BX 0+B0X), B+=AB0X+B(A0+X0)
A+B+
AB x = 0 x = 1 Z
00 00 10 0
01 11 01 0
11 01 10 1
10 10 11 0
(b) Z= (0)00101
(c) Propagation delay assumed to be zero.
Z
B
A
X
Pc
2. Do problem 13.5 on page 351 of your text.
(a) A+=AX0
2+AX1B0+X0
2X0
1+X0
2B0,B+=BX 0
1+BA0+X0
1A0
(b)
A+B+Z1Z2
AB X1X2= 00 01 11 10 X1X2= 00 01 11 10
00 11 01 00 10 10 10 00 00
01 11 01 01 01 00 11 11 00
11 11 01 00 10 00 00 00 00
10 10 00 10 10 00 01 01 00
S0
01/10
S1
S2
S3
01/01
00/00, 10/00, 11/01
00/00
11/00
11/00
00/10
00/00
01/00
01/11, 10/00,
11/11
10/00
10/00
pf2

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ECE 349 Homework Assignment #7 Solutions

Show your work! You will not receive full credit for the answer alone.

  1. Do problem 13.3 on page 350 of your text. (a) A+^ = A(B′^ + X) + A′(BX′^ + B′X), B+^ = AB′X + B(A′^ + X′)

A+B+ AB x = 0 x = 1 Z 00 00 10 0 01 11 01 0 11 01 10 1 10 10 11 0 (b) Z = (0)

(c) Propagation delay assumed to be zero.

Z

B

A

X

Pc

  1. Do problem 13.5 on page 351 of your text. (a) A+^ = AX 2 ′ + AX 1 B′^ + X 2 ′X′ 1 + X 2 ′B′, B+^ = BX 1 ′ + BA′^ + X 1 ′A′ (b) A+B+^ Z 1 Z 2 AB X 1 X 2 = 00 01 11 10 X 1 X 2 = 00 01 11 10 00 11 01 00 10 10 10 00 00 01 11 01 01 01 00 11 11 00 11 11 01 00 10 00 00 00 00 10 10 00 10 10 00 01 01 00

S 01/

S

S

S

01/

00/00, 10/00, 11/

00/

11/

11/ 00/ 00/ 01/

01/11, 10/00, 11/

10/

10/

  1. Do problem 13.6 on page 352 of your text.

Next State Z Present State X = 0 1 X = 0 1 S0 S0 S1 0 1 S1 S1 S2 1 0 S2 S2 S0 0 1 S3 S3 S0 1 0

S

S

S

S

0/

0/

0/

1/

1/

1/

1/ 0/

false

Z

X

clk

Q Q

  1. Do problem 13.9 on page 352 of your text. (a) Next State Z Present State X = 0 1 X = 0 1 S0 S1 S1 0 1 S1 S3 S3 0 1 S2 S4 S5 1 0 S3 S2 S3 1 0 S4 S1 S1 0 1 S5 S3 S3 0 1 S6 S4 S5 1 0 S7 S2 S3 1 0

0/0,

X Q Q

Z

Q

false

Clock

S

S1 S7 S2 S

S3 S5 S

0/

0/1 0/

1/

1/

0/0, 1/

0/0, 1/

0/0, 1/0 (^) 0/1 1/ 1/

1/

(c) Same, except for false output visible in timing diagram: 0 1 (0) 1 0 1 (d) Book suggests changing the input on falling edge of clock, but this could lead to metastability. We will discuss better methods in the next couple of weeks.