Homework Assignment for ECE2030A: Introduction to Computer Engineering - Fall 2008 - Prof., Assignments of Electrical and Electronics Engineering

A homework assignment for the course ece2030a: introduction to computer engineering at georgia tech, fall 2008. The assignment includes various problems related to boolean logic, digital design, and combinational logic. Students are required to use quine-mccluskey method, design logic circuits using nand and nor gates, complete sub-problems for a given pos representation, draw timing diagrams, design a bcd-style carryout and sum logic, and design a decoder for a seven-segment display. The assignment is worth a total of 100 points, with deadlines for each problem.

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ECE2030A Fall 2008 Prof. H.-H. S. Lee
Georgia Tech Page 1 of 4
ECE2030A Introduction to Computer Engineering
Fall 2008
Homework Assignment #2
Assigned 09/29/08 Due in the first 5 min in class 10/10/08
No late turn-in accepted
1. (20%) Use Quine-McClusey Method to simplify the following canonical SOP forms. Find all
the Essential Prime Implicants based the Q-M Method, and identify the non-Essential Prime
Implicants. List all possible solutions of your results.
1.1. 12,16) d(10,31) 30, 28, 21, 20, 17, 13, 11, 9, 8, 5, 4, 1, m(0,E)D,C,B,F(A, +=
1.2. 31) 28, 20, 16, 14, 10, 9, 5, d(1,30) 29, 27, 15, 12, 4, m(0,E)D,C,B,F(A, +=
2. (10%) Implement the following Boolean Expressions using Mixed Logic. For each equation,
show two implementations of the logic circuits either completely in NAND gates or completely
in NOR gates. Please discuss how many NAND (or NOR) gates are needed for each logic
circuit. For each gate, you are allowed to use any arbitrary number of inputs. Do not simplify
the equations, leave them intact.
2.1. DCBA F +=
2.2. BECDCBA F ++++=
3. (10%) For the given canonical POS representation below, please finish the sub-problems. You
can draw your Multiplexor and Decoder using block diagram with appropriate input and output
labels. In other words, you do not need to provide the design details within a MUX block or
Decoder block.
=15) 14, 12, 9, 7, 6, 3, M(2,D)C,B,F(A,
3.1. Design it using an 8-to-1 Multiplexor
3.2. Design it using a 4-to-16 Decoder and OR gates
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Georgia Tech Page 1 of 4

ECE2030A Introduction to Computer Engineering

Fall 2008

Homework Assignment

Assigned 09/29/08 Due in the first 5 min in class 10/10/ No late turn-in accepted

  1. (20%) Use Quine-McClusey Method to simplify the following canonical SOP forms. Find all the Essential Prime Implicants based the Q-M Method, and identify the non-Essential Prime Implicants. List all possible solutions of your results.

1.1. F(A, B,C,D,E)= ∑m(0,1,4,5,8,9,11,13,17,20,21,28,30,31)+d(10,12,16)

1.2. F(A, B,C,D,E)= ∑m(0,4,12,15,27,29,30)+d(1,5,9,10,14,16,20,28,31)

  1. (10%) Implement the following Boolean Expressions using Mixed Logic. For each equation, show two implementations of the logic circuits either completely in NAND gates or completely in NOR gates. Please discuss how many NAND (or NOR) gates are needed for each logic circuit. For each gate, you are allowed to use any arbitrary number of inputs. Do not simplify the equations, leave them intact. 2.1. F =A+B⋅C⋅D

2.2. F =A+B⋅C+D+C⋅E+B

  1. (10%) For the given canonical POS representation below, please finish the sub-problems. You can draw your Multiplexor and Decoder using block diagram with appropriate input and output labels. In other words, you do not need to provide the design details within a MUX block or Decoder block.

F(A,B,C,D)= ∏M(2,3,6,7,9,12,14,15)

3.1. Design it using an 8-to-1 Multiplexor 3.2. Design it using a 4-to-16 Decoder and OR gates

Georgia Tech Page 2 of 4

  1. (10%) Given the following combinational logic and input waveforms A, B, and CLK, draw the corresponding timing diagram for signal X1, X2 and F.

A

B

CLK F

X

X

CLK

B

A

Georgia Tech Page 4 of 4

  1. (30%) Seven-Segment Display. A DVD player display contains 5 different modes: On (ON), Off (OF), Stop (SP), Fast-forward (FF), and Play (PL). Using 2 seven-segment displays, each mode is encoded and illustrated in Figure 6(b). There are 5 push buttons that control the entering of the 5 states. Assume that when a button is pushed, the state will stay until another button is pushed. At any given time, only one button can stay pushed (or enabled). If more than one button is pushed simultaneously, the priority is determined as specified in Figure 6(b) and only the one with the highest priority will be enabled. To display correctly, you have to design a Decoder to convert a given push to the 14 control signals (A to G, 2 bits each) that control the 2 seven-segment displays. Please show and minimize your logic design of such a decoder. You can use any basic gates.

ON OFF FAST PLAY FORWARD

STOP

Higher Priority Lower Priority

A[0]

D[0]

E[0]

F[0] G[0]

B[0]

C[0]

A[1]

D[1]

E[1]

F[1] G[1]

B[1]

C[1]

ON OFF STOP FAST FWD PLAY

Your

Decoder

A[1:0] B[1:0] C[1:0] D[1:0] E[1:0] F[1:0] G[1:0]

14 7 7

Figure 6(a)

Figure 6(b)