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The final examination for a university course on mips pipelines and cache systems. The exam includes 7 problems covering various topics such as pipeline hazards, register renaming, tomasulo's algorithm, cache memories, and hard drives. Students are required to write down their thought process and assumptions, and the exam is open book and open notes. The allotted time is 50 minutes.
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Date: December 6, 2002 NAME: STUDENT CODE: Instructions: This exam is open book and open notes. Allotted time is 50 minutes. Explicitly state all your assumptions. Don’t just give answers, always try to write down the way you were thinking. Even if you can not find a solution, write down the paths you have tried. Good luck! Problem 1 (10 points) Consider the simple 5 stage MIPS pipeline. Which of the RAW, WAR and WAW hazards are possible? Explain both the yes and no answers. You might consider useful to make a simple drawing of the pipeline.
Consider the Tomasulo register renaming approach and the speculation approach as presented in the class. (a) Discuss the relative difficulty of their implementation. (b) Give reasons why register renaming was unsuccessful in the IBM 360/91 but it is widely used in current processors.
Cache memories are usually implemented in a static RAM technology. Main memories are usually dynamic RAM. Why does it still makes sense to have multiple cache levels when they are implemented in the same technology? Give reasons.
Concisely explain the difference between snooping and directory based cache coherence protocols.
A harddrive has a disk with a diameter of 3.5 inch, 120GB capacity, 6 surfaces, 24000 cylinders. Assume that only ¾ of the disk’s diameter is useful magnetic surface. (a) Compute the tracks per inch of this disk. (b) Compute the average bits per inch. (c) What is the bit density per unit area? (d) Propose a RAID configuration with which you would replace this disk (assume that both performance and reliability are important)