MIPS Pipeline, Lecture notes of Computer Architecture and Organization

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Hakim^ WeatherspoonCS^ 3410,

Spring^2012 Computer^ ScienceCornell^ University

MIPS^

Pipeline

See^ P&H^ Chapter

A^ Processor

alu

PC

imm memory

addrd d^ in^ out memory

offset^ target

=? cmpcontrol new^ pc

registerfile inst

extend Review:^ Single^ +4^ +

cycle^ processor

Review:

Single

Cycle

Processor

Advantages^ •^ Single

Cycle^ per

instruction

make^ logic

and^ clock

simple

Disadvantages^ •^ Since

instructions

take^ different

time^ to^ finish,^ memory

and^ functional

unit^ are not^ efficiently

utilized.

-^ Cycle^ time

is^ the^ longest

delay.

• Load^ instruction • Best^ possible

CPI^ is^1

• However,

lower^ MIPS

and^ longer

clock^ period

(lower^ clock

frequency);

hence,^ lower

performance.

Review:

Multi

Cycle

Processor

Advantages^ •^ Better

MIPS^ and

smaller^

clock^ period

(higher^ clock

frequency) • Hence,^ better

performance

than^ Single

Cycle^ processor

Disadvantages^ •^ Higher

CPI^ than

single^ cycle

processor

Pipelining:

Want^ better

Performance

-^ want^ small

CPI^ (close

to^ 1)^ with

high^ MIPS

and^ short

clock^ period

(high^ clock

frequency)

-^ CPU^ time

=^ instruction

count^ x^

CPI^ x^ clock

cycle^ time

The^ Kids

Alice Bob They^ don’t

always

get^ along…

The^ Bicycle

The^ Instructions

N^ pieces,

each^ built

following

same^ sequence:

Saw^

Drill^

Glue^

Paint

Design

1:^ Sequential

Schedule

Alice^ owns

the^ room

Bob^ can

enter^ when

Alice^ is

finished

Repeat^

for^ remaining

tasks

No^ possibility

for^ conflicts

Design

2:^ Pipelined

Design

Partition

room^ into

stages^

of^ a^ pipeline

One^ person

owns^ a

stage^ at

a^ time

4 stages 4 people working

simultaneously

Everyone

moves^

right^ in^

lockstep

Alice Bob Carol Dave

Pipelined

Performance

time 1 2

Latency:Throughput:Concurrency:

A^ Processor

alu

PC

imm memory

addrd d^ in^ out memory

offset^ target

=? cmpcontrol new^ pc

registerfile inst

extend Review:^ Single^ +4^ +

cycle^ processor

Write‐^ Back^17 Memory

InstructionFetch^

Execute

A registerfile control InstructionDecode

Processor

alu

imm

addrd d^ in^ out memory

inst memory PC

computejump/branchtargets

+4 new pc

extend

Time^ Graphs

1 2

3 4

5 6

7 8

9

Clock^ cycle IF^ ID^ Latency:Throughput:Concurrency:

MEMEX

WB

IF^ ID^

MEMEX

WB

IF^ ID^

MEMEX

WB

IF^ ID^

MEMEX

WB

IF^ ID^

MEMEX

WB

Principles

of^ Pipelined

Implementation

Break^ instructions

across^

multiple

clock^ cycles

(five,^ in

this^ case)

Design^

a^ separate

stage for

the^ execution

performed

during^

each^ clock

cycle

Add^ pipeline

registers

(flip‐flops)

to^ isolate

signals

between

different

stages