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PROGRAMMABLE PERIPHERAL
INTERFACE (PPI) -
- 8255 is a general purpose programmable device used
for data transfer between processor and I/O devices.
- It has 3 programmable I/O ports (PA,PB &PC) and
port operation (IN/OUT Port) is defined by control
word in the control word register.
- Ports are operated in two modes:
- i) I/O modes: Mode 0, Mode 1,& Mode 2
- Ii) BSR (Bit set/Reset) mode
About 8255
• PPI has 40 pins and it has three distinct modes of
operation.
• Port A (PA7-PA0) :8 pins
• Port B (PB7-PB0) :8 pins
• Port C (Pc: Upper: PC7-PC4) : 4 pins
• Port C (Pc: Lower: PC3-PC)) : 4 pins
• Data Bus (D7-D0) : 8 pins
• Control signals : 6 pins
• VCC and Gnd : 2 pins
Pin names and function
Pin name No.of pins
I/O functions
PA0-PA7 8 i/o
Tristate
Port can be configured either input or output by
software
Port has output latch buffer and input buffer
PA can be programmed by mode 0 , mode 1,
mode 2.
PB can be programmed by mode 0 and mode 1.
PC can be programmed by bit set/reset
operation.
Port C can be divided into two 4 bit ports namely
PC7-PC4 & PC3-PCO and used for control
signals to PA and PB
PB0-PB7 8 i/o
Tristate
PC0-PC7 8 i/o
Tristate
D0-D7 8 i/o
Tristate
Used for data transfer with MPU
Transfer of control words to PPI
Read status information from PPI
Group A and Group B control:
Group A and B get the Control Signal from CPU and send the command to the
individual control blocks.
Group A send the control signal to port A and Port C (Upper) PC7-PC4.
Group B send the control signal to port B and Port C (Lower) PC3-PC0.
operation modes: i) I/O modes (M0,M1,&M2)
ii) BSR (Bit set/Reset) mode
BIT SET/RESET MODE: The PORT C can be Set or Reset by sending OUT instruction to the CONTROL registers.
Mode 1:Handshake interrupt i/p port
When i/p device has data to send it checks if IBF (input buffer full)
signal is 0.
If 0, it sends data on PA/PB7-0 and activates STB* (Strobe) signal.
(STB* is active low. )
When STB* goes high, the data enters the port and IBF gets
activated.
If the Port interrupt is enabled, INT is activated. This interrupts the
processor.
Processor reads the port during the ISS. Then IBF and INT get
deactivated.
11
Handshake interrupt o/p port
When o/p device wants to receive data it checks if OBF (output buffer full) signal is 0.*
If 0, it receives data on PB7-0 and activates ACK (Acknowledge) signal. ACK is active low.**
When ACK goes high, the data goes out of the port and OBF is set to 1.**
If the Port interrupt is enabled, INT is activated. This interrupts the processor.
Processor sends another byte to the port during the ISS. Then OBF and INT are reset to 0.* 13
Mode 1 o/p mode
INTE A Controlled by bit set/reset of PC6. INTE B Controlled by bit set/reset of PC2.
82C55: Mode 2 Bi-directional Operation
- IBF : Input buffer full is an output indicating that the
input latch contains information for the external bi-
directional bus.
- INTE : Interrupt enable are internal bits that enable
the INTR pin. BIT PC6(INTE1) and PC4(INTE2).
- PC2,PC1,PC0 : These port C pins are general-purpose
I/O pins that are available for any purpose.
FOR BIT SET/RESET MODE (Port C only)
- This is bit set/reset control word format.
X X X
Don’t care
Bit select for Port C (Pc0-Pc7)
B 0
B 1
B 2
D7 D6 D5 D4 D3 D2 D1 D
BIT SET/RESET
1=SET
0=RESET
BIT SET/RESET FLAG
=0 Active
