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BCD Adder: VHDL Code and Waveform, Slides of Computer Science

Amity University - BiharComputer Science

The vhdl code for a binary coded decimal (bcd) adder, along with a waveform simulation. The code includes the entity and architecture definitions, as well as a component declaration for a 4-bit adder. The waveform shows the input bcd numbers, the intermediate sum, and the carryout for each step of the addition process.

Typology: Slides

2012/2013

Uploaded on 03/23/2013

dhruv
dhruv 🇮🇳

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bg1
BCD adder
K B3 B2 B1 B0 C D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
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BCD adder

K B3 B2 B1 B0 C D3 D2 D1 D

4-Bit adder

4-Bit adder

  • architecture Behavioral of BCDadder is
  • component adder4bit is
  • Port ( a : in std_logic_vector(3 downto 0);
  • b : in std_logic_vector(3 downto 0);
  • carryin : in std_logic;
  • sum : out std_logic_vector(3 downto 0);
  • carryout : out std_logic);
  • end component adder4bit;
  • signal s,x: std_logic_vector(3 Downto 0);
  • signal c,K : std_logic;
  • begin
  • u1:adder4bit port map(a(3)=>bcd1(3),a(2)=>bcd1(2),a(1)=>bcd1(1),a(0)=>bcd1(0),

b(3)=>bcd2(3),b(2)=>bcd2(2),b(1)=>bcd2(1),b(0)=>bcd2(0),

carryin=>bcdcarryin,sum(3)=>s(3),sum(2)=>s(2),sum(1)=>s(1),sum(0)=>s(0),carryout=>c);

  • K <= (s(3)and s(2))or(s(3)and s(1))or(c);
  • x <= "0110" when k ='1' else
  • "0000";
  • u2 :adder4bit port

map(a(3)=>s(3),a(2)=>s(2),a(1)=>s(1),a(0)=>s(0),b(3)=>x(3),b(2)=>x(2),b(1)=>x(1),b(0)=>x(0),carryin=>'0',

sum(3)=>bcdsum(3),sum(2)=>bcdsum(2),sum(1)=>bcdsum(1),sum(0)=>bcdsum(0),

carryout=>bcdcarryout);

  • end Behavioral;

Waveform of bcd adder