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VHDL Component Instantiation & Association Guide for Digital Circuit Creation, Slides of Computer Science

Amity University - Bihar Computer Science

An in-depth explanation of vhdl component instantiation and association techniques. It covers the concepts of positional and named association, rules for port maps, and examples of component instantiation using half adders and full adders. It also includes a 4-bit adder design using full adders. This information is essential for students and professionals working on digital circuit design projects using vhdl.

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2012/2013

Uploaded on 03/23/2013

dhruv 🇮🇳

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•Entity declaration

–describes the input/output ports of a module

entity reg4 is

port ( d0, d1, d2, d3, en, clk : in std_logic;

q0, q1, q2, q3 : out std_logic );

end entity reg4;

entity name port mode (direction)

port type

reserved words

punctuation

Port Name

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Entity declaration
- describes the input/output ports of a module

entity reg4 is port ( d0, d1, d2, d3, en, clk : in std_logic; q0, q1, q2, q3 : out std_logic ); end entity reg4;

entity name port mode (direction)

port type reserved words

punctuation

Port Name

Modeling Behavior

Architecture body
- describes an implementation of an entity
- may be several per entity
Behavioral architecture
- describes the algorithm performed by the module
- contains
  - process statements ,
  - Function
  - Statement
  - Port interface

Component Declaration

Component Component-name [is]

[ port (list-of-interface-port);]

End component [component-name];

Component-name: may or may not refer to the name of an entity already existing in a library.

Component cont..

List-of-interface-port specifies the name,mode, and type for each port of the component in a manner similar to that specified in an entity declaration.
The names of the ports may also be different from the names of the ports in the entity to which it may be bound.

Signal declaration

Are required to connect different types of ports.(mode of ports)
Class of the object identifier
Signal object should be same data type as it is in component and entity.
Signal object can be also be declared as an array

Component Instantiation

A Component instantiation statement defines a subcomponent of the entity in which it appears.
It associates the signals in the entity with the ports of that subcomponent.

Component instantiation

The component-name must be the name of a component declared earlier using a component declaration.
The association-list associates signals in the entity, called actuals, with the ports of a component, called formals.

Association technique

There are two ways to perform the association of formals with actuals: 1. Positional association 2. Named association

Named association

An association-list is of the form:

Formal 1 =>actual 1 ,formal 2 =>actual 2 ……..formaln=>actualn In named association, the ordering of the association is not important since the mapping between the actuals and formals is explicitly specified. The scope of the formals is restricted to be within the port map part of the instantiation for that component.

Rules of the port map

The types of the formal and actual being associated must be the same.
The modes of the ports must conform to the rule that if the formal s readable, so must the actual be; and if the formal is considered to be both readable and writeable, such a signal may be associated with a formal of any mode.

Circuit of Half adder

Circuit of Full adder

Example (Full adder using macro

of Half adder)

library ieee; use ieee.std_logic_1164.all;

entity ha is port ( x, y : in std_logic; s, c : out std_logic ); end ha;

architecture ha_behave of ha is begin s <= x xor y; c <= x and y; end ha_behave;

library ieee; use ieee.std_logic_1164.all; entity fa is port ( xin, yin, zin : in std_logic; cout, sum : out std_logic ); end fa; architecture fa_struct of fa is component ha is port ( x, y : in std_logic; s, c : out std_logic ); end component ha; signal temp0,temp1,temp2 : std_logic; begin ha1 : ha port map (x=>xin,y=>yin,s=>temp0,c=>temp1); ha2 : ha port map (x=>temp0,y=>zin,s=>sum,c=>temp2); cout <= temp1 or temp2; end fa_struct;