1
1. [add ext blankblank blank ]
Semantics: r1r0
r1r0
r3r2where r1r0means the 16-bit number formed by concatenating r1’s data
to r0’s data with the latter being the LS-byte and the
former
the MS-byte. (r2r3is similarly defined).
add ext opcode = 001111
2. (a) Design the format of a 24-bit instruction to perform a load word lw+ using the auto-increment
register-indirect addressing mode with the semantics ri
Mem
rj
;rj
rj
X. Note the initial (non-
incremented) value of rjis to be used for the address of the data word to be obtained from memory.
Clearly explain the format and what it means. Next, design the CU states for executing the lw+
instruction.
lw+ opcode = 010000
Hint: Just like in the sw instruction from Project 1, the 1st or least significant 2 bytes will have the
opcode and other information that the CU needs immediately to start processing the first part of the
instruction (ri
Mem
rj
). The last (most significant) 8 bits of the instruction can be fetched after
the initial part is done and loaded into an appropriate register (mdr, ir0, ir1, etc.) so that it enables the
2nd part of the instruction (rj
rj
X) to be completed.
(b) Comment on the speed efficiency of using the 24-bit lw+ instruction above versus using two 16-bit
instructions load ind and add imm (you did these in Project 1) to accomplish the same effect as the lw+
instruction.
3. [mul slow rirjrk] – type 1
Semantics: ri
rj
rkusing the slow multiplication technique given below (repeated addition with
no shifting). Note that either of rj,rkcould be negative.
mul slow opcode = 010001
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