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Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Lecture 4: Addressing modes g^ An instruction in the MC68000 contains two types of information^ n^ The type of operation to be performed^ n^ The location of the operand(s) on which to perform the function: the
addressing modes
g^ The MC68000 supports 14 different addressing modes^ n^ Data register direct^ n^ Address register direct^ n^ Absolute short^ n^ Absolute long^ n^ Register indirect^ n^ Post-increment register indirect^ n^ Pre-decrement register indirect^ n^ Register indirect with offset^ n^ Register indirect with index and offset^ n^ PC-relative with offset^ n^ PC-relative with index and offset^ n^ Immediate^ n^ Immediate quick^ n^ Implied register
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Addressing modes summary^ MODE^
ASSEMBLEREFFECTIVE ADDRESSSYNTAX GENERATIONData register direct D=Dn^ n
Address register direct^
A= An^ n
Absolute short^ xxx.S or <xxx
=(next word)
Absolute long^ xxx.L or >xxx
=(next two words)
Register indirect^
(A)^ =(A)n^ n^
Post-increment register indirect^
(A)+^ =(A), (A^ )โ(A)+Nn^ n^ n^ n^
Pre-decrement register indirect^
โ-(A) (A)(A)-N,=(An n n^
)n^
Register indirect with offset^
d^ (A)^ = (A)+d^16 n^ n^16
Register indirect with index and offset
d(A,X^ )^ = (A^8 nn^ n
)+ (X^ )+d^ n^8
PC-relative with offset^
d16(PC)^ = (PC)+d^16
PC-relative with index and offset^
d^ (PC,X^ )^ =PC+ (X^ )+d^8 n^ n^
8
Immediate^ #data (32 bits)
Data=next 2 word
Immediate quick^ #data (16 bits)
Data=next word
Implied register^ CCR,SR,SP,PC
= CCR,SR,SP,PC
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Address register direct g^ Description^ n^ address register (A0-A7) is the destination of data^ n^ only word or longword operands may be specified^ n^ a word operand is sign-extended to fit the register g^ Example^ n^ The contents of A3 are copied onto A0^ INSTRUCTION^
MOVEA.L^ A3,A0 MEMORY REGISTERADDRESS CONTENTS^ NAME^ CONTENTS
BEFORE^
A0^00200000 A30004F88A
AFTER^
A00004F88AA30004F88A
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Absolute short g^ Description^ n^ source or destination is a memory location whose address is specified in
one
extension word of the instruction^ g^ bits 16-23 of the full address are obtained by sign-extension of the 16-bit short address g Example n source is immediate, destination is absolute short address n since operation is^ โ.Wโ, source is sign-extended to two bytes INSTRUCTION^
MOVE.W^ #$1E,$800 MEMORY REGISTERADDRESS CONTENTS^ NAME^ CONTENTS
000800 BEFORE 000801
000800 AFTER 000801
00 1E
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Register indirect g^ Description^ n^ an^ address register^ contains the address of the source or destination operand g^ Example^ n^ The instruction moves a longword stored in D0 to the memory location specifiedby the address in A0^ INSTRUCTION^
MOVE.L^ D0,(A0) MEMORY REGISTERADDRESS CONTENTS^ NAME^ CONTENTS
001000001001 BEFORE 001002001003
5502 A0^00001000 3FD01043834F 00
001000001001 AFTER 001002001003
1043 A0^00001000 D01043834F 83 4F
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Post-increment register indirect g^ Description^ n^ indicated by a^ โ+โ^ sign^ after
(A)i^ n after reading or writing data the address register is incremented by the numberof bytes transferred g byte: [A ]โ[A]+1i i^ g word: [A ]โ[A]+2i i^ g longword: [A ]โ[A]+4i i^ MOVE.W (A5)+,D0 INSTRUCTION MEMORY^
REGISTER
ADDRESS^ CONTENTS^
NAME^ CONTENTS
001000001001 BEFORE 001002001003
4567 A5^0000100089 D00000FFFFAB
001000001001 AFTER 001002001003
4567 A5^0000100289 D0^00004567 AB
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Register indirect with offset g^ Description^ n^ a variation of register indirect that includes a 16-bit signed offset (displacement)as an extension word in the instruction^ n^ the sign-extended offset is added to the address register to form the effectiveaddress of the source or destination g^ Example^ n^ effective address is 6 plus address register^ n^ value stored in the address register does not change^ INSTRUCTION^
MOVE.W^ 6(A0),D0 MEMORY REGISTERADDRESS CONTENTS^ NAME^ CONTENTS
001026 BEFORE 001027
07 A0^00001020 BFD0^00000000
001026 AFTER 001027
07 A0^00001020 BFD0000007BF
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Register indirect with index and offset g^ Description^ n^ another variation of register indirect. An index register is used as well as an 8-bitsigned offset^ n^ the effective address is formed by adding the sign-extended offset, the contentsof the index register and the contents of the address register g^ Example^ n^ =$10+$100A+$2=$101C^ INSTRUCTION^
MOVEA^ $10(A0,D0.L),A1 MEMORY REGISTERADDRESS CONTENTS^ NAME^ CONTENTS
00101C BEFORE 00101D
A00000100AEFA1^0000000010 D0^00000002
00101C AFTER 00101D
A00000100AEFA1FFFFEF10 10 D0^00000002
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
PC-relative with index and offset g^ Description^ n^ an 8-bit signed offset plus an index register are used to compute the addressrelative to the PC^ INSTRUCTION^
MOVE.B^ TABLE(PC,D0.W),D0 MEMORY^ REGISTERADDRESS CONTENTS^ NAME^ CONTENTS
BEFORE^^001015
PC0000100A 19 D0ABCD
001015 AFTER
PC0000100E 19 D0^00000019
ORG^ $
00001000 303C 0005^2
MOVE.W^ #5,D
00001004 6100 0004^3
BSR^ SQUARE
00001008 4E75^4
RTS
0000100A^ 103B 0004^5
SQUARE^ MOVE.B^ TABLE(PC,D0.W),D
0000100E^ 4E75^6
RTS
TABLE^ DC.B^ 0,1,4,9,16,
END
Microprocessor-based System DesignRicardo Gutierrez-OsunaWright State University
Immediate g^ Description^ n^ immediate address uses^
two^ extension words to hold the source operand n data may be expressed in: g decimal (& prefix or none) g hexadecimal ($ prefix) g octal (@ prefix) g binary (% prefix) g ASCII (string within โโ) MOVE.L^ #$1FFFF,D0 INSTRUCTION MEMORY^
REGISTER
ADDRESS^ CONTENTS^
NAME^ CONTENTS
BEFORE^
DO^12345678
AFTER^
D0^ 0001FFFF
