An Autonomous Ins�tute
NEAR ITPB, CHANNASANDRA, BENGALURU – 560 067
Affiliated to VTU,Belagavi
Approved by AICTE, New Delhi
Recognized by UGC under 2(f) & 12(B)
Accredited by NBA & NAAC
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
Question Bank for Internal Assessment I
Odd Semester (2019-2020)
Sem VII Subject
Code
15CS72 Subject
Name
ADVANCED
COMPUTER
ARCHITECTURES
Duration 1Hr 30
Mins
Date Max.marks 30
Each Full Question below carries 15 Marks
CO Code Course Outcomes
402.2 Compare and contrast the parallel architectures
402.5 Measure performance parameters
Revised Bloom’s Taxonomy Levels: L1 – Remembering, L2 – Understanding, L3 – Applying,
L4 –Analyzing, L5 – Evaluating, and L6 - Creating
Q. No. MODULE - 2 MARKS CO Code Learning
Level
1 a List the characteristics of CISC and RISC architectures 7402.2 L1
1 b Illustrate Intel i860 processor architecture 8402.2 L2
2 a Explain the virtual memory models for multiprocessor system 9402.2 L2
2 b Compare Vector processor with symbolic processor 6402.2 L2
3 a Explain Superscalar Processors 8402.2 L2
3 b List the different hardware Technologies in Computer Architecture 7402.2 L1
4 a Explain the Representative of RISC scalar processor 9402.2 L2
4 b Illustrate the pipelining of superscalar processors 6402.2 L2
5 a Explain inclusion, coherence and locality properties 9402.2 L2
5 b Illustrate the pipelining in VLIW Processors 6402.2 L2
6 a Illustrate memory hierarchy technology 9402.2 L2
6 b Illustrate the pipelining in Vector Processors 6402.2 L2
Q. No. MODULE - 5 MARKS CO Code Learning
Level
1 a Explain the Languages and Compilers for parallel programming 8402.5 L2
bExplain types of dependencies in a Program 7402.5 L2
2 a Explain Parallel Program Development and Environment in Computer
Architecture
7402.5 L2
b Explain a) Reorder Buffer b)Register Renaming 8402.5 L2
3 a Explain Instruction and System Level Parallelism 7402.5 L2
