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Pipelining-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

Gujarat University Advanced Computer Architecture

This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Pipeline, Advance, Computer, Architecture, Design, Microprogram, Controller, Cycle, Datapath

Typology: Slides

2011/2012

Uploaded on 08/06/2012

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Recap: Lecture 9

Single cycle verses multi cycle datapath

Key components of multi cycle data path

Design and information flow in multi cycle

data path

Multi cycle control unit design

Finite State Machine–based control Unit

Microprogram-based controller

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Recap: Lecture 9

Single cycle verses multi cycle datapath

Key components of multi cycle data path

Design and information flow in multi cycle

data path

Multi cycle control unit design

Finite State Machine – based control Unit

Microprogram-based controller

What is pipelining?

Pipelining is a fundamental concept

It utilizes capabilities of the Datapath by

Sequential Laundry

T a s k O r d e r

B

C

D

A

Time

6 PM

2 AM

Explanation next please ……………..

Pipelined Laundry: Start work ASAP

Pipelined laundry takes 3.5 hours for 4

loads!

T a s k O r d e r

12 2 AM

6 PM

Time

A

B

C

D

Pipelining Lessons

Pipeline rate limited by:

- Slowest pipeline stage

- Time to “ fill ” pipeline and time to “ drain ” it

reduces speedup

- Unbalanced lengths of pipe stages reduces

speedup

If washer takes longer time than the dryer then

dryer has to wait!

Stall for Dependences

Five Steps of Datapath

Ins. fetch

Dec/Reg

Exec

Mem

Wr

Pipeline Control

IR <- Mem[PC];

PC < – PC+4;

A <- R[rs];

B< – R[rt]

S < –

A + B;

R[rd] < – S;

S < –

A + SX;

M < – Mem[S]

R[rd] < – M;

S < – A or

ZX;

R[rt] < – S;

S < –

A + SX;

Mem[S] <- B

If Cond

PC <

PC+SX;

Instruction Fetch

ID/Reg. Rd

Exe/Address

Memory Rd/Wrt

Reg. Wrt (WB)

Pipelined Registers Included

A

B

Reg

File

IRex

Dcd Ctrl

Exec

S

IRmem

Ex Ctrl

Reg.

File

Equal

WB

Ctrl

Mem

Access

Data

Mem

M

I

Rwb

Mem Ctrl

Next PC

IR

Inst. Mem

Instruction

Fetch

ID/Register

Read

Execute/

Address

Memory

Rd/Wrt

Write Back

(Reg. Wrt)

Multiple Cycle verses Pipeline – Pipeline enhances performance

5 6 7 8 9 10

Clk

Cycle 2 3 4

Multiple Cycle Implementation:

Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem

Load Store

Ifetch

R-type

Reg Exec Mem

Load

Ifetch Reg Exec Mem Wr

Pipeline Implementation:

Ifetch Reg Exec Mem Wr

Store

Ifetch Reg Exec Mem Wr

R-type

Explanation next slide…….

3 Instructions program reconsidered

Load

Store

R-type (ADD)

Another Example

Consider a multicycle, unpiplined processor requires 4 cycles

for the ALU and Branch operations and 5 cycles for the memory

operation.

Assume the relative frequency of these operations is 40%, 25%

and 35% respectively; and the clock cycle is of 1 n sec.

In pipelined implementation, due to clock skew and setup

processor adds 0.2 n sec. to the clock

Ignoring any latency impact, how much is the

speedup from the pipelined processor?

Solution

Unpiplined Processor:

Average Execution Time/Instruction = Clock Cycle x Average CPI

= 1 n sec. x [{(0.4 +.25)} x 4 + 0.35 x 5]

= 1 n sec x (0.65 x 4 + 0.35 x 5)

= 1 n sec. x (2.60 + 1.75)

= 4.35 n sec

Pipelined Processor:

Average Execution Time/ Instruction = Clock cycle + overhead

= 1 n sec. + 0.2 n. sec

= 1.2 n sec

Speed up = 4.35 / 1.2 = 3.62 times

Graphical Representation

Explanation…… Next Please

Time

(clock cycles)

I.Mem

Instr 1

Instr 2

Instr 3

Instr 4

ALU

I.Mem

Reg

D. Mem

ALU

I.Mem

Reg

D. Mem

Reg

ALU

I.Mem

Reg

D.Mem

Reg

ALU

D.Mem

Reg

ALU

I.Mem

Reg

Mem

Reg

Instr 5

CC

CC4 CC

CC7 CC

CC

Reg

Why Pipeline?

Because the resources are there!

I

O

Time (clock cycles)

Inst 0

Inst 1

Inst 2

Inst 4

Inst 3

ALU

Im Reg

Dm Reg

ALU

Im Reg

Dm Reg

ALU

Im Reg

Dm Reg

ALU

Im Reg

Dm Reg

ALU

Im Reg

Dm Reg

Pipelining-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

Related documents

Partial preview of the text

Download Pipelining-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity!

Recap: Lecture 9

Single cycle verses multi cycle datapath

Key components of multi cycle data path

Design and information flow in multi cycle

data path

Multi cycle control unit design

Finite State Machine – based control Unit

Microprogram-based controller

What is pipelining?

Pipelining is a fundamental concept

It utilizes capabilities of the Datapath by

Sequential Laundry

B

C

D

A

Time

6 PM

2 AM

Pipelined Laundry: Start work ASAP

Pipelined laundry takes 3.5 hours for 4

loads!

12 2 AM

6 PM

Time

A

B

C

D

Pipelining Lessons

Pipeline rate limited by:

- Slowest pipeline stage

- Time to “ fill ” pipeline and time to “ drain ” it

reduces speedup

- Unbalanced lengths of pipe stages reduces

speedup

If washer takes longer time than the dryer then

dryer has to wait!

Stall for Dependences

Five Steps of Datapath

Ins. fetch

Dec/Reg

Exec

Mem

Wr

Pipeline Control

Instruction Fetch

ID/Reg. Rd

Exe/Address

Memory Rd/Wrt

Reg. Wrt (WB)

Pipelined Registers Included

A

B

S

WB

M

I

IR

Multiple Cycle Implementation:

Pipeline Implementation:

Another Example

Consider a multicycle, unpiplined processor requires 4 cycles

for the ALU and Branch operations and 5 cycles for the memory

operation.

Assume the relative frequency of these operations is 40%, 25%

and 35% respectively; and the clock cycle is of 1 n sec.

In pipelined implementation, due to clock skew and setup

processor adds 0.2 n sec. to the clock

Ignoring any latency impact, how much is the

speedup from the pipelined processor?

Solution

Unpiplined Processor:

Average Execution Time/Instruction = Clock Cycle x Average CPI

= 1 n sec. x [{(0.4 +.25)} x 4 + 0.35 x 5]

= 1 n sec x (0.65 x 4 + 0.35 x 5)