Role of Petri Nets in Asynchronous Hardware Design: History, Principles, and Applications, Slides of Electronic Circuits Design

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Advanced Tutorial on Hardware

Design and Petri nets

Jordi Cortadella Univ. Politècnica de Catalunya

Luciano Lavagno Università di Udine

Alex Yakovlev Univ. Newcastle upon Tyne

Tutorial Outline

Introduction

• Modeling Hardware with PNs
• Synthesis of Circuits from PN specifications
• Circuit verification with PNs
• Performance analysis using PNs

Role of Hardware in modern systems

• Technology soon allows putting 1 billion

transistors on a chip

• Systems on chip is a reality – 1 billion operations

per second

• Hardware and software designs are no longer

separate

• Hardware becomes distributed, asynchronous

and concurrent

Role of Hardware design tools

• Design productivity is a problem due to chip

complexity and time to market demands

• Need for well-integrated CAD with simulation,

synthesis, verification and testing tools

• Modelling of system behaviour at all levels of

abstraction with feedback to the designer

• Design re-use is a must but with max technology

independence

Why Petri nets are good

• Finite State Machine is still the main formal tool in hardware design but it may be inadequate for distributed, concurrent and asynchronous hardware
• Petri nets:
  • simple and easy to understand graphical capture
  • modelling power adjustable to various types of behaviour at different abstraction levels
  • formal operational semantics and verification of correctnes (safety and liveness) properties
  • possibility of mechanical synthesis of circuits from net models

A bit of history of their marriage

• 1950’s and 60’s: Foundations (Muller & Bartky, Petri, Karp & Miller, …)
• 1970’s: Toward Parellel Computations (MIT, Toulouse, St. Petersburg, Manchester …)
• 1980’s: First progress in VLSI and CAD, Concurrency theory, Signal Transition Graphs (STGs)
• 1990’s: First asynchronous design (verification and synthesis) tools: SIS, Forcage, Petrify
• 2000’s: Powerful asynchronous design flow

What is an asynchronous circuit

• No global clock; circuits are self-timed or self-clocked
• Can be viewed as hardwired versions of parallel and distributed programs – statements are activated when their guards are true
• No special run-time mechanism – the “program statements” are physical components: logic gates, memory latches, or hierarchical modules
• Interconnections are also physical components: wires, busses

Synchronous Design

Register Sender Logic^

Register Receiver

Clock

Data

Data input

Clock

Tsetup Thold

Timing constraint: input data must stay unchanged within a setup/hold window around clock event. Otherwise, the latch may fail (e.g. metastability)

Physical (Analogue) level

• Strict view: an asynchronous circuit is a (analogue) dynamical system – e.g. to be described by differential equations
• In most cases can be safely approximated by logic level (0-to-1 and 1-to-0 transitions) abstraction; even hazards can be captured
• For some anomalous effects, such as metastability and oscillations, absolute need for analogue models
• Analogue aspects are not considered in this tutorial (cf. reference list)

Logical Level

• Circuit behaviour is described by sequences of up (0-to-
  1. and down (1-to-0) transitions on inputs and outputs
• The order of transitions is defined by causal relationship, not by clock ( a causes b, directly or transitively)
• The order is partial if concurrency is present
• A class of async timed (yet not clocked!) circuits allows special timing order relations ( a occurs before b, due to delay assumptions )

Simple circuit example

req x y

req a b^ +

req

C

ack

ack2 (^) ack out

out=(x+y)*(a+b)

x

y a b

out

Data flow graph

Simple circuit example

req x y

req a b^ +

req

C

ack

ack2 (^) ack out

out=(x+y)*(a+b)

x

y a b

out

Data flow graph (^) Control flow graph – Petri net

req

req

ack

ack

req3 (^) ack

Muller C-element

Key component in asynchronous circuit design – like a Petri net transition

C

x y x

y=x1*x2+(x1+x2)y Set-part (^) Reset-part

Muller C-element

Key component in asynchronous circuit design – like a Petri net transition

C

x y x

y=x1*x2+(x1+x2)y Set-part (^) Reset-part

0 0

0