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A step-by-step tutorial on using altera quartus ii development software to design and implement full adders and 4-bit adders, as well as a 16-bit multiplexer using schematics and block diagrams. The tutorial covers creating new projects, adding components, ports, and connections, compiling designs, and simulating the results.
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The Quartus II development softwareprovides a
complete design environment
for FPGA designs.
Design entry using schematics, blockdiagrams, VHDL, and Verilog HDL.
Design analysis and synthesis, fitting,assembling, timing analysis, simulation.
Open Quartus II and pick a device.
Build a full adder.
(Block/Schematic)
z
Add components
z
Add ports
z
Add connections
(single wire connection)
Build a 4-bit adder.
z
Create a block for full adder
z
Use conduit and port mapping
z
Compile the 4-bit adder.
z
Open compiler tool
z
Read compilation report
z
Open timing closure floorplan
z
Simulate the 4-bit adder.
z
Open simulator tool
z
Edit simulation waveform
z
Observe simulation results
z
Schematic for 16-bit Multiplexer
z
Use connections by name
z
Menu
Æ
File
Æ
New Project Wizard
z
Menu
File
New
z
Create a Block Diagram/Schematic File
z
Menu
File
Save As: fadder.bdf
LibraryNew BlockSingle WireBusConduit
Place two
xor
, two
and
and one
or
.
z
Find
input
and
output
under
primitives
Æ
pin
,
and place three
input
and two
output
z
Double click on each pin, to change pin name.
z
Menu
File
New
z
Create a Block Diagram/Schematic File
z
Menu
File
Save As: adder4.bdf
z
Click on new block
, and draw a block.
z
Double click on the block name, change it to
fadder
z
Click on
to dismiss the
properties window.
z
Right click on the block, andselect
AutoFit
in the pop-up
menu.
z
Select the block, make fourcopies by copy/paste.
z
Add 3 inputs and 2 outputs.
z
Use conduit tool to connect each
fadder
to inputs and
outputs. Conduit can stop at any point on a blockborder.
z
For A[3..0], B[3..0] and S[3..0], port mapping should bemanually defined. Edit the
signals
property for A[3..0]
like this:
z
After port mapping for A[3..0], B[3..0] and S[3..0], youwill see this: