+ Bộ cộng 1bit
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(
a,b,cin : in std_logic;
sum,cout : out std_logic
);
end fulladder ;
architecture C of fulladder is
Begin
sum <= a xor b xor cin;
cout <= ( a and b ) or ( b and cin) or ( a and cin) ;
End C ;
+ Bộ cộng 4bit
library ieee;
use ieee.std_logic_1164.all;
entity fulladder4bit is
port(
A,B : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Sum,Cout : out std_logic_vector(3 downto 0)
);
end fulladder4bit ;
architecture B of fulladder4bit is
component fulladder is
port(
a,b,cin : in std_logic;
sum,cout : out std_logic);
end component;
signal C: std_logic_vector(3 downto 0);
Begin
bit0: fulladder port map(A(0),B(0),Cin,Sum(0),C(0));
bit1: fulladder port map(A(1),B(1),C(0),Sum(1),C(1));
bit2: fulladder port map(A(2),B(2),C(1),Sum(2),C(2));
bit3: fulladder port map(A(3),B(3),C(2),Sum(3),C(3));
Cout <= C;
End B ;
+ Bộ trừ 1bit
+ Bộ trừ 4bit: làm giống bộ cộng
+ Mux2to1
library ieee;
use ieee.std_logic_1164.all;
