Analog to Digital Conversion-Embedded System Control-Lecture Slides, Slides of Embedded Control Systems

This lecture was delivered by Mr. Rohit Kohli at National Institute of Industrial Engineering for Embedded System Control course. It includes: Muscular, Dysrophies, Papillae, G-protein, Genetic, Myoblasts, Myotubes, Eccentrically, Milestones, Nutrition

Typology: Slides

2011/2012

Uploaded on 07/26/2012

unknown user
unknown user 🇮🇳

1 / 5

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
2
Analog to Digital Conversion
zResolution
zAnalog Input Channels
zConversion time
zVref
zDigital data Output
zStart and End of conversion Signals
docsity.com
pf3
pf4
pf5

Partial preview of the text

Download Analog to Digital Conversion-Embedded System Control-Lecture Slides and more Slides Embedded Control Systems in PDF only on Docsity!

Analog to Digital Conversion z

Resolution

z

Analog Input Channels

z

Conversion time

z

Vref

z

Digital data Output

z

Start and End of conversion Signals

docsity.com

Registers for Serial Communication z

A/D Result High Register (ADRESH)

z

A/D Result Low Register (ADRESL)

z

A/D Control Register 0 (ADCON0)

z

A/D Control Register 1 (ADCON1)

z

A/D Control Register 2 (ADCON2)

ADCON0 RegisterADCON1 Register 7

CHS

CHS

CHS

CHS

GO/DONE

ADON

VCFG

VCFG

PCFG

PCFG

PCFG

PCFG0docsity.com

Steps to configure ADC 1. Configure the A/D module:

z

Configure analog pins, voltage reference and digital I/O (ADCON1)

z

Select A/D input channel (ADCON0)

z

Select A/D conversion clock (ADCON2)

z

Select A/D acquisition time (ADCON2)

z

Turn on A/D module (ADCON0)

  1. Configure A/D interrupt (if desired):

z

Clear ADIF bit

z

Set ADIE bit

z

Set GIE bit

  1. Wait the required acquisition time (if required). 4. Start conversion:

z

Set GO/DONE bit (ADCON0 register)

  1. Wait for A/D conversion to complete, by either:

z

Polling for the GO/DONE bit to be cleared OR

z

Waiting for the A/D interrupt

  1. Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. 7. For next conversion, go to step 1 or step 2, as required. The A/D conversion

time per bit is defined as TAD. A minimum wait of 2 TAD is required beforethe next acquisition starts.

docsity.com

SUMMARY

docsity.com