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2 ■ Solutions to Case Studies and Exercises
A.1 The first challenge of this exercise is to obtain the instruction mix. The instruction frequencies in Figure A.27 must add to 100, although gap and gcc add to 100.2 and 99.5 percent, respectively, because of rounding error. Because each total must in reality be 100, we should not attempt to scale the per instruction average frequen- cies by the shown totals of 100.2 and 99.5. However, in computing the average fre- quencies to one significant digit to the right of the decimal point, we should be careful to use an unbiased rounding scheme so that the total of the averaged fre- quencies is kept as close to 100 as possible. One such scheme is called round to even, which makes the least significant digit always even. For example, 0.15 rounds to 0.2, but 0.25 also rounds to 0.2. For a summation of terms, round to even will not accumulate an error as would, for example, rounding up where 0.15 rounds to 0. and 0.25 rounds to 0.3. For gap and gcc the average instruction frequencies are shown in Figure S.12.
The exercise statement gives CPI information in terms of four major instruction categories, with two subcategories for conditional branches. To compute the
Instruction Average of gap and gcc % load 25. store 11. add 20. sub 2. mul 0. compare 4. load imm 3. cond branch 10. cond move 0. jump 0. call 1. return 1. shift 2. and 4. or 8. xor 2. other logical 0.
Figure S.12 MIPS dynamic instruction mix average for gap and gcc.
Appendix A Solutions (by Rui Ma and Gregory D. Peterson)
Appendix A Solutions ■ 3
average CPI we need to aggregate the instruction frequencies in Figure S.12 to match these categories. This is the second challenge, because it is easy to mis- categorize instructions. The four main categories are ALU, load/store, condi- tional branch, and jumps. ALU instructions are any that take operands from the set of registers and return a result to that set of registers. Load/store instructions access memory. Conditional branch instructions must be able to set the program counter to a new value based on a condition. Jump-type instructions set the pro- gram counter to a new value no matter what. With the above category definitions, the frequency of ALU instructions is the sum of the frequencies of the add, sub, mul, compare, load imm (remember, this instruction does not access memory, instead the value to load is encoded in a field within the instruction itself), cond move (implemented as an OR instruction between a controlling register and the register with the data to move to the desti- nation register), shift, and, or, xor, and other logical for a total of 48.5%. The fre- quency of load/store instructions is the sum of the frequencies of load and store for a total of 37.6%. The frequency of conditional branches is 10.7%. Finally, the frequency of jumps is the sum of the frequencies of the jump-type instructions, namely jump, call, and return, for a total of 3.0%. Now
A.2 See the solution for A.1 (above) for a discussion regarding the solution methodol- ogy for this exercise. As with problem A.1, the frequency of ALU instructions is the sum of the fre- quencies of the add, sub, mul, compare, load imm (remember, this instruction does not access memory, instead the value to load is encoded in a field within the instruction itself ), cond move (implemented as an OR instruction between a con- trolling register and the register with the data to move to the destination register), shift, and, or, xor, and other logical for a total of 51.1%. The frequency of load/ store instructions is the sum of the frequencies of load and store for a total of 35.0%. The frequency of conditional branches is 11.0%. Finally, the frequency of jumps is the sum of the frequencies of the jump-type instructions, namely jump, call, and return, for a total of 2.8%.
Effective CPI Instruction category frequency ×Clock cycles for category categories
=( 0.485) ( 1.0) + ( 0.367) ( 1.4) + ( 0.107) ( (0.6 ) (2.0 ) +( 1 – 0.6) ( 1.5)) + ( 0.03) +( 1.2) =1.
CPI =1.0 ×51.1% +1.4 ×35.0% +2.0 ×11.0% ×60% +1.5 ×11.0% ×40% +1.2 ×2.8% =1.
Appendix A Solutions ■ 5
ALU instructions: (17.8% + 3.0% + 0.6% + 5.6% + 1.0% + 0.9% + 4.1%) = 33.0% Load-stores: (9.4% + 2.4%) = 11.8% Conditional branches: 1.0% Jumps: 0% FP add: (8.6% + 6.2%) = 14.8% Load-store FP: (16.5% + 11.6%) = 28.1% Other FP: (1.4% + 0.4% + 0.4% + 0.8%) = 3.0% CPI = 1.0 × 33.0% + 1.4 × 11.8% + 2.0 × 1.0% × 60% + 1.5 × 1.0% × 40% + 6. × 8.2% + 4.0 × 14.8% + 20 × 0.2% + 1.5 × 28.1% + 2.0 × 3.0% = 2.
A.4 This exercise is similar to A.3.
And 0. Or 4. Xor – other logical – load FP 16. store FP 11. add FP 8. sub FP 6. mul FP 8. div FP 0. move reg-reg FP 1. compare FP 0. cond mov FP 0. other FP 0.
Figure S.14 MIPS dynamic instruction mix for lucas and swim.
Instruction Average of applu and art % Load 16. Store 1. Add 30. Sub 1. Mul 1. Compare 3. load imm 6. cond branch 7. cond move 0. Jump –
Figure S.15 Continued
6 ■ Solutions to Case Studies and Exercises
ALU instructions: (30.2% + 1.2% + 1.2% + 3.7% + 6.8% + 0.2% + 0.4% + 1.0% + 1.6%) = 46.3% Load-stores: (16.0% + 1.4%) = 17.4% Conditional branches: 7.0% Jumps: 0% FP add: (3.4% + 1.4%) = 4.8% Load-store FP: (11.7% + 4.4%) = 16.1% Other FP: (0.8% + 0.4% + 0.3%) = 1.5% CPI = 1.0 × 46.3% + 1.4 × 17.4% + 2.0 × 7.0% × 60% + 1.5 × 7.0% × 40% + 6.0 × 6.4% + 4.0 × 4.8% + 20 × 0.4% + 1.5 × 16.1% + 2.0 × 1.5% = 1. A.5 Take the code sequence one line at a time.
Call – Return – Shift 0. And – Or 1. Xor 1. other logical – load FP 11. store FP 4. add FP 3. sub FP 1. mul FP 6. div FP 0. move reg-reg FP 0. compare FP 0. cond mov FP 0. other FP –
Figure S.15 MIPS dynamic instruction mix for applu and art.
- A = B + C ;The operands here are given, not computed by the code, so copy propagation will not transform this statement.
- B = A + C ;Here A is a computed value, so transform the code by substituting A = B + C to get = B + C + C ;Now no operand is computed
- D = A – B ;Both operands are computed so substitute for both to get = (B + C) – (B + C + C) ;Simplify algebraically to get = – C ;This is a given, not computed, operand
8 ■ Solutions to Case Studies and Exercises
Since MIPS instructions are 4 bytes in size, code size is the number of instructions times 4: Instruction bytes = 4 × 18 = 72
b. This problem is similar to part (a), but with x86-64 instructions instead. The number of instructions executed dynamically is the number of initializa- tion instructions plus the number of instructions in the loop times the number of iterations: Instructions executed = 3 + (13 × 101) = 1316 A.8 This problem focuses on the challenges related to instruction set encoding. The length of the instructions are 12 bits. There are 32 registers so the length of the register field will be 5 bits for each register operand. We use addr[11] to addr[0] to represent the 12 bits of the address as shown in the tables below. a. In the first case, we need to support 3 two-address instructions. These can be encoded as follows:
addr[11:10] addr[9:5] addr[4:0]
3 two-address instr. '00', '01', '10' '00000' to '11111' '00000' to '11111'
Other instructions '11' '00000' to '11111' '00000' to '11111'
ex_b_7: movq $0x0,%rax # rax = 0, initialize i = 0 movq $0x0,%rbp # base pointer = 0 movq %rax,0x1b58(%rbp) # store i to location 7000 ($1b58) movq 0x1388(%rbp),%rdx # load C from 5000 ($1388) loop: movq 0x1b58(%rbp),%rax # get value of i mov %rax,%rbx # rbx gets copy of i shl $0x3,%rbx # rbx now has i * 8 movq 0x0bb8(%rbx),%rcx # load B[i] (3000 = $0bb8) to rcx add %rdx,%cdx # B[i] + C mov %rax,%rbx # rbx gets copy of i shl $0x3,%rbx # rbx now has i * 8 movq %rcx,0x03e8(%rbx) # A[i] ← B[i] + C (base address of A is 1000) movq 0x1b58(%rbp),%rax # get value of i add $0x1,%rax # increment i movq %rax,0x1b58(%rbp) # save i cmpq $0x0065,%rax # is counter at 101 ($0065)? jae loop # if not 101, repeat
Figure S.17 x86 code to implement the C loop without using registers to hold updated values for future use or to pass values to a subsequent loop iteration.
Appendix A Solutions ■ 9
Hence, for the one-address and two-address instructions must be mapped to the remaining 10 bits with the upper two bits encoded as ‘11’. The one- address instructions are then encoded with the addr[9:5] field using ‘00000’ to ‘11101’ for the 30 instruction types, leaving the addr[4:0] field or the regis- ter operand. This leaves the patterns with ‘11’ followed by ‘11110’ in the upper seven bits and ‘00000’ to ‘11111’ in the lower five bits to encode 32 of the zero-address instructions. The remaining zero-address instructions can be encoded using ‘11’ followed by ‘11111’ in the upper seven bits and ‘0000’ to ‘01100’ in the lower five bits to encode the other 13 zero-address instructions.
Hence, it is possible to have the above instruction encodings. b. This scenario is similar to above, with the two-address instructions encoded with the upper two bits as ‘00’ to ‘01’. The one-address instructions can be encoded with the upper two bits as ‘11’ and using ‘00000’ to ‘11110’ to dif- ferentiate the 31 one-address instructions. The pattern ‘11’ and ‘11111’ in the upper seven bits is then used to encode the zero-address instructions, with the lower five bits to differentiate them. We can only encode 32 of these patterns, not the 35 that are required; hence, it is impossible to have these instruction encodings. c. In this part, we already have encoded three two-address instructions as above. Moreover, we have 24 zero-address instructions encoded as below with ‘00000’ in the addr[9:5] field and ‘00000’ to ‘10111’ in the addr[4:0] field. We would like to fit as many one-address instructions as we can. Note that we cannot take advantage of any of the unused encodings with ‘11’ and ‘00000’ in the upper seven bits because we would need to use the entire addr[4:0] field for the single address of the operand. Hence, we can use the encodings with ‘00001’ to ‘11111’ in addr[9:5] for the one-address instructions and save the last five bits for the register address. Because this includes 31 patterns, we can support up to 31 one-address instructions. Note that we could also add up to eight additional zero-address instructions if we wish as well.
addr[11:10] addr[9:5] addr[4:0]
3 two-address instr. '00', '01', '10' '00000' to '11111' '00000' to '11111'
30 one-address instr. '11' '00000' to '11101' '00000' to '11111'
45 zero-address instr. '11' '11110' '00000' to '11111'
'11' '11111' '00000' to '01100'
addr[11:10] addr[9:5] addr[4:0]
3 two-address instr. '00', '01', '10' '00000' to '11111' '00000' to '11111'
24 zero-address instr. '11' '00000' '00000' to '10111'
X one-address instr. '11' '00001' to '11111' '00000' to '11111'
Appendix A Solutions ■ 11
- Stack
The total code size is 672/8 = 84 bytes. The number of bytes of data moved to or from memory is 576/8 = 72 bytes. There are 3 overhead instructions. The number of overhead data bytes is 24 bytes.
- Accumulator
The total code size is 576/8 = 72 bytes. The number of bytes of data moved to or from memory is 512/8 = 64 bytes. There is 1 overhead instruction. The number of overhead data bytes is 8 bytes.
Code
Destroyed data Overhead
Code size (bits)
Size of mem data Push A no 72 64 Push B no 72 64 Add A and B 8 Pop C C 72 64 Push E no 72 64 Push A no yes 72 64 Sub A and E 8 Pop D D 72 64 Push C no yes 72 64 Push D no yes 72 64 Add C and D 8 Pop F no 72 64 Total 672 576
Code
Destroyed data Overhead
Code size (bits)
Size of mem data
Load A 72 64
Add B A 72 64
Store C 72 64
Load A C yes 72 64
Sub E A 72 64
Store D 72 64
Add C D 72 64
Store F 72 64
Total 576 512
12 ■ Solutions to Case Studies and Exercises
- Register-memory
The total code size is 564/8 = 71 bytes. The number of bytes of data moved to or from memory is 384/8 = 48 bytes. There is no overhead instruction. The number of overhead data bytes is 0 bytes.
- Register-register
The total code size is 546/8 = 69 bytes. The number of bytes of data moved to or from memory is 384/8 = 48 bytes. There is no overhead instruction. The number of overhead data bytes is 0 bytes. A.10 Reasons to increase the number of registers include:
- Greater freedom to employ compilation techniques that consume registers, such as loop unrolling, common subexpression elimination, and avoiding name dependences.
- More locations that can hold values to pass to subroutines.
- Reduced need to store and re-load values.
Code
Destroyed data Overhead
Code size (bits)
Size of mem data Load R1, A 78 64 Add R3, R1, B 84 64 Store R3, C 78 64 Sub R2, R1, E 84 64 Store R2, D 78 64 Add R4, R3, R2 84 Store R4, F 78 64 Total 564 384
Code
Destroyed Data Overhead
Code size (bits)
Size of mem data Load R1, A 78 64 Load R2, B 78 64 Add R3, R1, R2 26 Store R3, C 78 64 Load R4, E 78 64 Sub R5, R1, R4 26 Store R5, D 78 64 Add R6, R3, R5 26 Store R6, F 78 64 Total 546 384
14 ■ Solutions to Case Studies and Exercises
As with the 32-bit processor, two bytes are added after the bool b so the int c is aligned and two more are added after the short e so the float f is aligned. Finally, the final int x has four bytes added to the end to make the struct aligned with an 8 byte boundary. Hence, the original struct requires 56 bytes on a 64-bit processor. By reordering the contents of the struct in the same manner as with the 32-bit machine above, the additional padding requirements are eliminated and the 48 byte size can be achieved for the struct. A.12 No solution provided. A.13 No solution provided. A.14 No solution provided. A.15 No solution provided. A.16 No solution provided. A.17 No solution provided. A.18 Accumulator architecture code: Load B ;Acc ← B Add C ;Acc ← Acc + C Store A ;Mem[A] ← Acc Add C ;Acc ← "A” + C Store B ;Mem[B] ← Acc Negate ;Acc ← − Acc Add A ;Acc ← “− B” + A Store D ;Mem[D] ← Acc Memory-memory architecture code: Add A, B, C ;Mem[A] ← Mem[B] + Mem[C] Add B, A, C ;Mem[B] ← Mem[A] + Mem[C] Sub D, A, B ;Mem[D] ← Mem[A] − Mem[B] Stack architecture code: (TOS is top of stack, NTTOS is the next to the top of stack, and * is the initial contents of TOS) Push B ;TOS ← Mem[B], NTTOS ← * Push C ;TOS ← Mem[C], NTTOS ← TOS Add ;TOS ← TOS + NTTOS, NTTOS ← * Pop A ;Mem[A] ← TOS, TOS ← * Push A ;TOS ← Mem[A], NTTOS ← * Push C ;TOS ← Mem[C], NTTOS ← TOS Add ;TOS ← TOS + NTTOS, NTTOS ← * Pop B ;Mem[B] ← TOS, TOS ← * Push B ;TOS ← Mem[B], NTTOS ← * Push A ;TOS ← Mem[A], NTTOS ← TOS Sub ;TOS ← TOS − NTTOS, NTTOS ← * Pop D ;Mem[D] ← TOS, TOS ← * Load-store architecture code: Load R1,B ;R1 ← Mem[B] Load R2,C ;R2 ← Mem[C]
Appendix A Solutions ■ 15
Add R3,R1,R2 ;R3 ← R1 + R2 = B + C Add R1,R3,R2 ;R1 ← R3 + R2 = A + C Sub R4,R3,R1 ;R4 ← R3 − R1 = A − B Store A,R3 ;Mem[A] ← R Store B,R1 ;Mem[B] ← R Store D,R4 ;Mem[D] ← R
A.19 This problem is similar to A.7, but students are asked to consider how to implement a looping structure for the different architecture styles as in problem A.18. We assume A, B, C, and i are held in memory using addresses 1000, 3000, 5000, and 7000 as in problem A.7. For the register-register case, we can use the MIPS code from A.7. In this case we assume the locations for each of the variables as with A.7.a. ex_19_1: DADD R1,R0,R0 ;R0 = 0, initialize i = 0 SW 7000(R0),R1 ;store i loop: LD R1,7000(R0) ;get value of i DSLL R2,R1,#3 ;R2 = word offset of B[i] DADDI R3,R2,#3000 ;add base address of B to R LD R4,0(R3) ;load B[i] LD R5,5000(R0) ;load C DADD R6,R4,R5 ;B[i] + C LD R1,7000(R0) ;get value of i DSLL R2,R1,#3 ;R2 = word offset of A[i] DADDI R7,R2,#1000 ;add base address of A to R SD 0(R7),R6 ;A[i] ← B[i] + C LD R1,7000(R0) ;get value of i DADDI R1,R1,#1 ;increment i SD 7000(R0),R1 ;store i LD R1,7000(R0) ;get value of i DADDI R8,R1,#-101 ;is counter at 101? BNEZ R8,loop ;if not 101, repeat For the register-memory case, we can use the x86-64 code as in A.7 b): ex_7_2: movq $0x0,%rax # rax = 0, initialize i = 0 movq $0x0,%rbp # base pointer = 0 movq %rax,0x1b58(%rbp) # store i to location 7000 ($1b58) movq 0x1388(%rbp),%rdx # load C from 5000 ($1388) loop: movq 0x1b58(%rbp),%rax # get value of i mov %rax,%rbx # rbx gets copy of i shl $0x3,%rbx # rbx now has i * 8 movq 0x0bb8(%rbx),%rcx # load B[i] (3000 = $0bb8) to rcx add %rdx,%cdx # B[i] + C mov %rax,%rbx # rbx gets copy of i shl $0x3,%rbx # rbx now has i * 8 movq %rcx,0x03e8(%rbx) # A[i] ← B[i] + C (base address of A is 1000)
Appendix A Solutions ■ 17
each instruction includes two words, one for the opcode and the other for the immediate value. We can then use loadind in which the value in the accumulator is used as the address for the load and store as before in which the value in the accumulator is stored to a direct address (but we modify the address in the code to patch it to what we need at the time). ex_7_4: load 0 # put 0 in acc store i # save i loop: load i # put i in acc shl 3 # shift left by three (multiply by 8) store tmp # temporary storage for i* load tmp # get i8 in acc add 1000 # get address for A[i] store Aaddress # store to immediate value for instruction at label Astore load tmp # get i8 in acc add 3000 # compute address of B[i] loadind # use indirect addressing to get B[i] add C # get sum of B[i] + C Astore: storeind # store to location in immediate value of this instruction load i # get value of i add 1 # increment by one store i # save value of i cmp 101 # compare i to 101 jle # jump to next iteration if i <= 100
A.20 The total of the integer average instruction frequencies in Figure A.28 is 99%. The exercise states that we should assume the remaining 1% of instructions are ALU instructions that use only registers, and thus are 16 bits in size. a. Multiple offset sizes are allowed, thus instructions containing offsets will be of variable size. Data reference instructions and branch-type instructions con- tain offsets; ALU instructions do not and are of fixed length. To find the aver- age length of an instruction, the frequencies of the instruction types must be known. The ALU instructions listed in Figure A.28 are add (19%), sub (3%), com- pare (5%), cond move (1%), shift (2%), and (4%), or (9%), xor (3%), and the unlisted miscellaneous instructions (1%). The cond move instruction moves a value from one register to another and, thus, does not use an offset to form an effective address and is an ALU instruction. The total frequency of ALU instructions is 47%. These instructions are all a fixed size of 16 bits. The remaining instructions, 53%, are of variable size. Assume that a load immediate (load imm) instruction uses the offset field to hold the immediate value, and so is of variable size depending on the magni- tude of the immediate. The data reference instructions are of variable size and
18 ■ Solutions to Case Studies and Exercises
comprise load (26%), store (10%), and load imm (2%), for a total of 38%. The branch-type instructions include cond branch (12%), jump (1%), call (1%), and return (1%), for a total of 15%. For instructions using offsets, the data in Figure A.31 provides frequency information for offsets of 0, 8, 16, and 24 bits. Figure 2.42 lists the cumula- tive fraction of references for a given offset magnitude. For example, to deter- mine what fraction of branch-type instructions require an offset of 16 bits (one sign bit and 15 magnitude bits) find the 15-bit magnitude offset branch cumulative percentage (98.5%) and subtract the 7-bit cumulative percentage (85.2%) to yield the fraction (13.3%) of branches requiring more than 7 mag- nitude bits but less than or equal to 15 magnitude bits, which is the desired fraction. Note that the lowest magnitude at which the cumulative percentage is 100% defines an upper limit on the offset size. For data reference instruc- tions a 15-bit magnitude captures all offset values, and so an offset of larger than 16 bits is not needed. Possible data-reference instruction sizes are 16, 24, and 32 bits. For branch-type instructions 19 bits of magnitude are necessary to handle all offset values, so offset sizes as large as 24 bits will be used. Pos- sible branch-type instruction sizes are 16, 24, 32, and 40 bits. Employing the above, the average lengths are as follows.
b. With a 24-bit fixed instruction size, the data reference instructions requiring a 16-bit offset and the branch instructions needing either a 16-bit or 24-bit off- set cannot be performed by a single instruction. Several alternative imple- mentations are or may be possible. First, a large-offset load instruction might be eliminated by a compiling opti- mization. If the value was loaded earlier it may be possible, by placing a higher priority on that value, to keep it in a register until the subsequent use. Or, if the value is the stored result of an earlier computation, it may be possi- ble to recompute the value from operands while using no large-offset loads. Because it might not be possible to transform the program code to accom- plish either of these schemes at lower cost than using the large-offset load, let’s assume these techniques are not used. For stores and branch-type instructions, compilation might be able to rear- range code location so that the store effective address or target instruction address is closer to the store or branch-type instruction, respectively, and thus require a smaller offset. Again, let’s assume that this is not attempted.
ALU length = 16 bits Data-reference length = 16 × 0.304 + 24 × (0.669 – 0.304) + 32 × (1.0 – 0.669) = 24.2 bits Branch-type length = 16 × 0.001 + 24 × (0.852 – 0.001) + 32 × (0.985 – 0.852) = 25.3 bits Average length = 16 × 0.47 + 24.2 × 0.38 + 25.3 × 0. = 20.5 bits
20 ■ Solutions to Case Studies and Exercises
c. With a 24-bit fixed offset size, the ALU instructions are 16 bits long and both data reference and branch instructions are 40 bits long. The number of instructions fetched is the same as for byte-variable-sized instructions, so the per-instruction bytes fetched is (16 bits/instr)(0.47) + (40 bits/instr)(0.38 + 0.15) = 3.59 bytes/instr. This is less that the bytes per original instruction fetched using the limited 8- bit offset field instruction format. Having an adequately sized offset field to avoid frequent special handling of large offsets is valuable. A.21 No solution provided. A.22 Same as HP3e problem 2. a.
b.
c. 4F4D, 5055, and 5455. Other misaligned 2-byte words would contain data from outside the given 64 bits. d. 52 55 54 4D, 55 54 4D 50, and 54 4D 50 43. Other misaligned 4-byte words would contain data from outside the given 64 bits. A.23 [Answers can vary.] ISAs can be optimized for a variety of different problem domains. We consider different features in ISA design, considering typical applications for desktop, server, cloud, and embedded computing, respectively.
- For desktop, we care about the speed of both the integer and floating-point units, but not as much about the power consumption. We also would consider the compatibility of machine code and the software running on top of it (e.g., x code). The ISA should be made capable of handling a wide variety of applica- tions, but with commodity pricing placing constraints on the investment of resources for specialized functions.
- For servers, database applications are typical, so the ISA should be targeting integer computations, with support for high throughput, multiple users, and virtu- alization. ISA design can emphasize integer operations and memory operations. Dynamic voltage and frequency scaling could be added for reduced energy con- sumption.
43 4F 4D 50 55 54 45 52
C O M P U T E R
45 52 55 54 4D 50 43 4F
E R U T M P C O
Appendix A Solutions ■ 21
Cloud computing ISAs should provide support for virtualization. Integer oper- ation and memory management will be important. Power savings and facilities for easier system monitoring will be important for large data centers. Security and encryption of user data will be important, so ISAs may provide support for these concerns.
Power consumption is a big concern in embedded computing. Price is also important. The embedded ISAs may provide facilities for sensing and controlling devices with special instructions and/or registers, analog to digital and digital to analog converters, and interfaces to specialized, application-specific functions. The ISA may omit floating point, virtual memory, caching, or other performance optimizations to save energy or cost.
