PowerPC Architecture and Assembly Language
• Overview
• Loads and Stores
• Arithmetic and Logical Operations
• Shifts and Rotates
• Branches
Reference:
Chapters 3 and 4 of PowerPC manual
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PowerPC Arch. & Assembly: Overview of Loads, Stores, Arithmetic, Logic, Shifts, & Branches, Slides of Microcontrollers
An overview of the powerpc architecture and assembly language, focusing on loads and stores, arithmetic and logical operations, shifts and rotates, and branches. It includes examples and references to the powerpc manual on docsity.com.
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2012/2013
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PowerPC Architecture and Assembly Language
• Overview
• Loads and Stores
• Arithmetic and Logical Operations
• Shifts and Rotates
• Branches
Reference:
Chapters 3 and 4 of PowerPC manual
Instruction Set Architectures
An Instruction Set Architecture (ISA) defines an interface between software and hardware:
- Specifies processor aspects visible to programmer
- number and size of registers
- precise semantics and encoding of instructions
- Not tied to a particular implementation (microarchitecture)
instructions registers memory
- (r4) means the contents of register 4.
- (x)0 indicates x 0's in a row.
- 0x5555 means 5555 16 just as it does in C/C++.
- The symbol || means concatenation.
- Ex: 15||0x0000 would be the same as 0xF0000.
- MEM(x,y) is a reference to y bytes at memory location x.
- r4[x-y] is a reference to bits x though y of register 4.
- Register bits are numbered from 0 (MSB) to 31 (LSB).
- Note that this is the OPPOSITE of MIPS/LC
Databook notation (a sampling)
Example
addi r5, r0, 0 loop: lbz r4, 0(r3) add r5, r4, r addi r3, r3, 1 b loop
Add an (infinite) set of bytes beginning at the byte-address stored in register r3. Result in r5, which we initialize to zero.
Example (cont’d)
add r5, r4, r
- add a register
- r5 (r4) + (r6)
Example (cont’d)
addi r3, r3, 1
- add an i mmediate value. If second arg is r0 treat as zero.
- r3 (r3) + 1
b loop
- b ranch to label loop
- machine language actually encodes offset -16 (well – 4 ) (Why?)
Zeroing vs. Algebraic Loads
lhz r4, 0(r3) : halfword in (r3)+0 is loaded into low 16 bits of r4; remaining bits in r4 are cleared.
lha r4, 0(r3) : halfword in (r3)+0 is loaded into low 16 bits of r4; remaining bits in r4 are filled with copy of MSB in loaded halfword. (aka ―sign-extended‖)
The algebraic option is
- not allowed for byte loads (use extsb instruction)
- illegal for word loads on 32-bit implementations
Update Mode
lwzu r4, 4(r3)
effective address (r3) + 4 r4 MEM (EA, 4) r3 effective address
In English: Load from the effective address, as usual AND Update the base register to hold the effective address
Where would you expect to see this?
Aligned Big-Endian Mapping
struct{ int a; /* 0x1112_1314 word / double b; / 0x2122_2324_2526_2728 double word / char c; /* 0x3132_3334 word / char d[7]; / ‗L‘, …, ‗R‘ array of bytes / short e; / 0x5152 half word / int f; / 0x6162_6364 word */ } S;
11 12 13 14 21 22 23 24 25 26 27 28 31 32 33 34 L M N O P Q R 51 52
00 01 02 03 04 05 06 07
61 62 63 64 20 21 22 23 24 25 26 27
address (hex) contents contents contents contents contents address (hex)
Arithmetic and Logical Instructions
- Most have two versions:
- Register-register add r1, r2, r3 means r1 (r2) + (r3)
- Immediate (suffix i ) addi r1, r3, 5 means r1 (r3) + 5
- Immediate operands are limited to 16 bits
- Immediates are always expanded to 32 bits for processing. Arithmetic operations (+, -, *, /) sign extend the immediate. Logical operations (and, or, etc) zero extend the immediate.
Dealing with 32-bit Immediates
Two ways for loading a full 32-bit value into a register:
lis r3, 5 lis r3, 5 ori r3, r3, 99 addi r3, r3, 99
When are these two approaches not equivalent?
Sub, Mult, and Div
- Subtraction: subf means sub tract f rom
- subf r3, r4, r5 results in r3 = r5 – r
- subfic is immediate version; ‗c‘ indicates carry flag is set
- sub, subi are simplified mnemonics
- numerous other add/sub variants deal with carry flag for extended precision
- Multiply
- Issue: product of two 32-bit numbers is 64 bits
- mulli, mullw generate lower 32 bits of product
- mulhw, mulhwu generate upper 32 bits of product
- Divide
- divw, divwu for signed/unsigned division
Example Revisited
list: .byte 0x20,4,-12,
main: lis r3, list@h ori r3, r3, list@l addi r5, r0, 0 addi r3, r3, - addi r6, r0, 0 loop: lbzu r4, 1(r3) add r5, r4, r addi r6, r6, 1 cmpwi r3, 4 beq done b loop
done: b done
A more complete version of the example the earlier slide that initializes the address and stops at the end of the list
There is an error in this code… Can you find it?
New Instructions
cmpwi r3, 4
- c o mp are w ord i mmediate
- Sets three condition code bits in Condition Register (CR): LT, GT, EQ
beq done
- b ranch if eq ual
- Branches if (EQ==1)
Assembler suffixes:
- @h
- @l