–1–
CSC/ECE 506: Architecture of Parallel Computers
Problem Set 1
Due Friday, June 7, 2002
Problems 2, 3, and 5 will be graded. There are 60 points on these problems
. Note: You must do
all the problems, even the non-graded ones
. If you do not do some of them, half as many points
as they are worth will be subtracted from your score on the graded problems.
Problem 1.
(15 points)
Page 12 of the lecture notes for Lecture 3 (titled
Communication
architectures, cont.
) presents an assembly-language version of the inner loop of a vector-
processor matrix-multiplication program whose pseudocode is given on page 10 of the same
lecture. Write the assembly code for the entire program (i.e., the program on page 10), using the
code already given on page 12. Please make sure that your program is well commented;
however, you do not have to comment portions that you use without change from page 12.
Problem 2.
(15 points)
Suppose a program that was being run on one processor is now run on
a 100-processor machine. If a speedup of 80 is desired (on the 100-processor machine, as
compared to the single processor), what fraction of the program can be serial? Use Amdahl’s law.
Problem 3.
(25 points)
Main memory for a processor consists of 1,024K words (220 addresses).
We would like to design a cache that contains 16K words (214 addresses) that minimizes the
average access time (AAT) for a given program. There are 16 words per cache line.
(a) How many cache lines are there?
(b) If a direct-mapped cache is used, how many bits make up the tag field?
(c) Consider a program that accesses the following 16 hexadecimal memory words in sequence:
5A000
5A010
5A020
5A030
4A000
4A010
4A020
4A030
5A000
5A010
5A020
5A030
4A000
4A010
4A020
4A030
Fill in the following table with the tag values and the first word on the line for each of the first four
cache lines, after the program makes the above 16 memory accesses.
