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CS365 1
Arithmetic and Logic Unit
CS 365 Lecture 5
Prof. Yih Huang
CS365 2
Inside a Processor
Data Cache Instruction Cache
(Internal) Bus
Integer Arithmetic Circuits
Floating Point Arithmetic Circuits
Branch
Control
Logic
Registers
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CS365 Lecture 5: Arithmetic and Logic Unit, Study notes of Computer Architecture and Organization
A part of the lecture notes for cs365, covering the arithmetic and logic unit (alu) of a processor. It explains the concept of alu, its components such as data and instruction caches, buses, registers, and arithmetic circuits. It also covers the representation of signed numbers using two's complement method and the detection of overflows.
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CS365 1
Arithmetic and Logic Unit
CS 365 Lecture 5 Prof. Yih Huang
CS365 2
Inside a Processor
Data Cache Instruction Cache
(Internal) Bus
Integer Arithmetic Circuits
Branch Floating Point Arithmetic Circuits
Control Logic
Registers
CS365 3
Arithmetic and Logic Unit (ALU)
The part of a processor circuit that actually gets the computations done.
32
32
32
operation
result
a
b
ALU
CS365 4
Bits are just bits (no inherent meaning) Binary numbers (base 2) ⇒ decimal: 0...2n- ASCII codes Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers How do we represent negative numbers?
Numbers
CS365 7
0000 0000 0000 0000 0000 0000 0000 0000 = 0 0000 0000 0000 0000 0000 0000 0000 0001 = + 0000 0000 0000 0000 0000 0000 0000 0010 = + ... 0111 1111 1111 1111 1111 1111 1111 1110 = +2,147,483, 0111 1111 1111 1111 1111 1111 1111 1111 = +2,147,483, 1000 0000 0000 0000 0000 0000 0000 0000 = –2,147,483, 1000 0000 0000 0000 0000 0000 0000 0001 = –2,147,483, 1000 0000 0000 0000 0000 0000 0000 0010 = –2,147,483, ... 1111 1111 1111 1111 1111 1111 1111 1101 = – 1111 1111 1111 1111 1111 1111 1111 1110 = – 1111 1111 1111 1111 1111 1111 1111 1111 = –
32-bit Signed Numbers
Two’s Complement (^) Decimal
CS365 8
Negating a two's complement number: invert all bits and add 1
- remember: “negate” and “invert” are different! Exercises (in 6 bits)
- Negate 12
- Negate -
Two's Complement Operations
CS365 9
Sign Extensions
MIPS 16 bit immediate gets converted to 32 bits for arithmetic copy the most significant bit (the sign bit) into the other bits
4 bit number 8 bit equivalent
CS365 10
Additions & Subtractions
Just like regular binary numbers
CS365 13
Architecture and case dependent Solution 1: just remember it and leave the handing to software.
- The condition/flag register of IA Solution 2: exception/interrupt
- Control jumps to predefined address for exception
- Interrupted address is saved for possible resumption
- Used by MIPS
Effects of Overflow
CS365 14
Discussion
IA32 provides an addc (add with carry) instruction. What is its use?
CS365 15
Problem: Consider a logic function with three inputs: A, B, and C.
Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true
Show the truth table for these three functions. Show the Boolean equations for the three functions. Show an implementation consisting of inverters, AND, and OR gates
Review: Boolean Algebra & Gates
CS365 16
Design An Overflow Detector
Inputs: SA (sign of A), SB (Sign of B), OP (operation, 0 for add, 1 for sub). Output: OF=0 no overflow, 1 overflow Truth Table: Boolean equation for OF. A circuit design of OF according to the equation above. 1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
OP SA SB OF
CS365 19
Second Exercise
Let us build a one-bit ALU to support addition and logic or.
- Operation: 0 for add 1 for or operation
result
a
b
ALU
CS365 20
Solution
Truth Table
Sum of product
CS365 21
Supporting MIPS Logic Instructions
MIPS provides bit-wise and, or, xor, and nor instructions. Input operation (3 bits) determine the output. operation
result
a
b
ALU
3
CS365 22
32-bit ALU
Both inputs A and B are 32 bit wide.
- Size of the truth table?
Rather we will just cascade 32 1-bit ALU.
- How about carries?
- We need to refine the spec of the 1-bit ALU
CS365 25
Building a 32-bit ALU
b
0
2
R esu lt
O pe ration
a
1
C arryIn
C a rryO ut a 3 1b 3 1 R e s u lt 3 1
R e s u lt 0
C a r r y In a 0 b 0
a 1b 1 R e s u lt 1
a 2b 2 R e s u lt 2
O p e r a t io n
A L U 0
C a r r y In C a r r y O u t
A L U 1
C a r r y In C a r r y O u t
A L U 2
C a r r y In C a r r y O u t
A L U 3 1
C a r r y In
CS365 26
Two's complement approach: negate b and add. How do we negate?
A clever solution:
What about subtraction (a – b)?
0
2
Result
Operation
a
1
CarryIn
CarryOut
0 1
Binvert
b
CS365 27
Need to support the set-on-less-than instruction (slt)
- remember: slt is an arithmetic instruction
- produces a 1 if rs < rt and 0 otherwise
- use subtraction: (a-b) < 0 implies a < b Need to support test for equality (beq $t5, $t6, offset)
- use subtraction: (a-b) = 0 implies a = b
Tailoring the ALU to the MIPS
CS365 28
Supporting slt
0 3
R e s ult
O p e ra tio n
a
1 C arr yIn C ar ryO u t
B in v e rt^01
b^
2
L es s
0 3
R e s u lt
O p e r atio n
a
1 C ar ryI n
B in ve rt^01
b^
2
Le ss
S e t
O v e rflo w d e tec tio n
O ve rflo w
a. b.
CS365 31
Important points about hardware
- all of the gates are always working
- the speed of a gate is affected by the number of inputs to the gate
- the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)
- What is the critical path in our 32-bit ALU?
CS365 32
Ripple Carry Adder Is Slow
Logic circuit speed is determined by the number of gates a signal have to pass in the worst case. Assuming each 1-bit ALU adds x –gate delay, what is the delay of a 32-bit ALU?
CS365 33
Carry Look Ahead A^ B^ Cout
0 0 0 “kill” 0 1 Cin “propagate” 1 0 Cin “propagate” A0B0 G S 1 1 1 “generate” P G = A and B A1B1 G S P = A xor B P A B
S GP
A B
S GP
Cin
C1 =G0 + C0 P
C2 = G1 + G0 P1 + C0 P0 P
C3 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P G
C4 =...
P
CS365 34
16-Bit Adder
CarryIn
Re sult0--
CarryIn^ ALU
Re sult4--
CarryInALU
Re sult8--
CarryInALU
Ca rryOu t
Re sult12--
CarryInALU
C1 C2 C3 C P0G0 P1G1 P2G2 P3G
p ig i ci + 1 p i + 1g i + 1ci + 2 pi + 2gi + 2ci + 3 p i + 3g i + 3ci + 4
a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 a12 b12 a13 b13 a14 b14 a15 b
Carry-loo kahead un i
t
CS365 37
Unsigned Combinational Multiplier
Stage i accumulates A * 2 i^ if Bi == 1
B 0
A 3 A 2 A 1 A 0
A 3 A 2 A 1 A 0
A 3 A 2 A 1 A 0
A 3 A 2 A 1 A 0
B 1
B 2
B 3
P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0
0 0 0 0
CS365 38
Discussions
Multiplication is expensive A combinational multiplier uses a great deal of silicon
- 32 32-bit adders needed We will discuss designs that are slower but less silicon demanding.
- Due to its complexity, we will first present a basic but suboptimal design, and refine it twice.
CS365 39
Shift and Add
One step per clock tick; n clock cycles needed for n -bit multiplications
A 3 A 2 A 1 A (^0) B 0 A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0
B 1
B 2 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0
0 0 0 0 0 0 0 Clock tick
Clock tick Clock tick
Clock tick
CS365 40
Example: 0101 ×××× 0011
Product
Multiplicand
To add or not to add
Multiplier