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Main points of this exam paper are: Arithmetic, Pass-Transistor Logic, Downwards, Shifter Network, Implemented, Minimum-Size Transistors, Worst-Case Delay
Typology: Exams
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University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh3:30-5pm e141@eecs
For all problems, you can assume the following transistor parameters:
NMOS:
VT n = 0.75V, k’n = 20 μA/V^2 , λ = 0, γ= 0.5 V1/2, 2Φ (^) F = -0.6V
PMOS:
VT p = -0.75V, k’p = 7 μA/V^2 , λ = 0, γ= 0.5 V1/2, 2Φ (^) F = -0.6V
Last First
GRAD/UNDERGRAD
Problem 1: Arithmetic
Jane Doe, a UC Berkeley EECS 141 is requested to design a logarithmic shifter based on pass-transistor logic that takes as input a 16-bit word and supports a programma- ble shift to the right (i.e. downwards) between 0 and 15 bit.
a. Assume that the shifter network is implemented using minimum-size transistors with the following parameters: Req = 10 kΩ, Cdb = Csb = 10 fF, Cgb = 15 fF (all other capaci- tances may be ignored). The capacitance at the output node equals 50 fF. Draw the resis- tor-capacitor network that represents to the worst-case delay of the network , and annotate the meaningful component values. Give a first-order approximation of the delay of the network. No buffering should be included at this point.
b. Jane has heard (on the grapevine) that the worst-case delay of the network can be reduced by introducing buffers in the network. She decides to introduce two buffers. Her library supports a buffer with a delay of 400 psec (independent of the load - waw!) and an input capacitance and output capacitance of 20 fF. Draw a diagram indicating where she should introduce the buffers. Derive an expression for the worst-case delay of the network and determine its value.
tp =
tp =
PROBLEM 3: Sequential Circuits
Consider the sequential circuit shown below.
a. Fill in the missing clock connections on the schematics (marked by the gray boxes) so that the circuit will operate correctly. For each connection you can choose between φ and φ(you may assume here that they are non-overlapping and that there is no skew).
b. For each gate in the circuit, fill in the operation mode of the gate for the given clock mode in the table below (choose between precharge , eval , and hold ).
c. The above circuit has some room for simplification. Describe in a couple of sentences how you would simplify the circuit (and the resulting benefit) without sacrificing func- tional correctness.
Gate 1 Gate 2 Gate 3 Gate 4 φ φ
VDD VDD VDD
Out
VDD
A (^) Out
Gate 1 (^) Gate 2 Gate 3 (^) Gate 4
PROBLEM 4: Logic styles and power
A designer has to implement a 6-input AND gate. He has available a library containing the cell-types enumerated below together with their properties in terms of capacitance.
a. Determine the average power dissipation of an implementation using a 6-input NAND (and an inverter). The circuit operates at a supply voltage of 3V and a clock frequency of 20 MHz. Assume that all the inputs have an equal chance of being 0 or 1. You may ignore the power dissipated by the 6 input signals.
b. Implement the same function using predominantly 3-input NANDs (plus some others gates). Draw the schematic of the circuit you will be using and determine the power dissi- pation.
Inv NOR2 NOR3 NAND2 NAND3 NAND Cin 48 fF 48 fF 48 fF 48 fF 48 fF 48 fF Cout 85 fF 101 fF 117 fF 105 fF 132 fF 200 fF
Pav =
Pav =
