Building an Arithmetic Logic Unit (ALU) for MIPS: Logic Gates, Adders, and Subtraction, Slides of Computer Science

An in-depth exploration of building an arithmetic logic unit (alu) for the mips instruction set. Topics include logic gates, half-adders and full-adders, ripple carry adders, faster adders, and tailoring the alu to support subtraction and set-on-less-than (slt) instructions.

Typology: Slides

2012/2013

Uploaded on 03/22/2013

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Arithmetic II
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Download Building an Arithmetic Logic Unit (ALU) for MIPS: Logic Gates, Adders, and Subtraction and more Slides Computer Science in PDF only on Docsity!

Arithmetic II

CPSC 321

Today’s Menu

Arithmetic-Logic Units

Logic Design Revisited

Faster Addition

Multiplication (if time permits)

Logic Gates

  • AND gate
  • OR gate
  • NOT gate

What are the truth tables?

Logic Gates

  • NOR gate
  • NAND gate
  • XOR gate

What are the truth tables? Docsity.com

Full Adder

cin a b c (^) out s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

Give a Boolean formula for s

  • s=cin xor a xor b

Give a Boolean formula for c (^) out

  • cout =ab+cin (a xor b)

Design now a circuit using and, or, xor.

Full Adder

c in

a

b

c out

s

s=c in xor a xor b c out = ab+c in (a xor b)

Critical Path

c in

a

b

c out

s

Suppose that each gate has a unit delay. What is the critical path (= path with the longest delay)? Docsity.com

Ripple Carry Adders

  • Each gates causes a delay
    • our example: 3 gates for carry generation
    • book has example with 2 gates
  • Carry might ripple through all n adders
    • O(n) gates causing delay
    • intolerable delay if n is large
  • Carry lookahead adders

Fast Adders

Iterate the idea, generate and propagate

ci+1 = g (^) i + pici

= g (^) i + pi(g (^) i-1 + pi-1 ci-1 ) = gi + pig (^) i-1 + pipi-1 ci- = g (^) i + pig (^) i-1 + pipi-1 g (^) i-2 +…+ p (^) ipi-1 …p 1 g (^0) +pipi-1 …p 1 p 0 c 0

Two level AND-OR circuit

Carry is known early!

Carry Lookahead Adders

  • Based on the previous identity

Fast because critical path is shorter O(log n) gate delays [assuming 2-input gates] More complex to implement Design is less regular Layout of one bit adder cells depend on i

  • Compromise

couple blocks of carry lookahead adders

Tailoring the ALU to the MIPS

  • Need to support the set-on-less-than instruction (slt)
    • remember: slt is an arithmetic instruction
    • produces 1 if rs < rt and 0 otherwise
    • use subtraction: (a-b) < 0 implies a < b
  • Need to support test for equality (beq $t5, $t6, $t7)
    • use subtraction: (a-b) = 0 implies a = b

SLT

  • Determine a<b
  • Calculate b-a
  • If MSB equals
    • 1, then a<b
    • 0, then a>=b
  • Changes?
    • Operation less than
    • Output of subtraction
    • Overflow

0

2

Result

Operation

a

1

CarryIn

CarryOut

0 1

Binvert

b

a31 0 Set

ALU0 Result

CarryIn

a

a1 0 Result

a2 0 Result

Operation

b

b

b

b

Result Overflow

Binvert

CarryIn

Less

CarryIn CarryOut

CarryInALU1Less CarryOut

CarryInALU2Less CarryOut

CarryInALU31Less

  • LSB indicates

whether a<b

  • 0 if false
  • 1 if true

Test for equality

  • Notice control lines:

000 = and 001 = or 010 = add 110 = subtract 111 = slt

  • Note: zero is a 1 when the result is zero! a31 0 Set

a0 Result

a1 Result 0

a2 Result 0

Operation

b

b

b

b

Result Overflow

Bnegate

Zero

CarryIn ALU0Less CarryOut

CarryInALU1Less CarryOut

CarryInALU2Less CarryOut

CarryInALU31Less