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An in-depth exploration of building an arithmetic logic unit (alu) for the mips instruction set. Topics include logic gates, half-adders and full-adders, ripple carry adders, faster adders, and tailoring the alu to support subtraction and set-on-less-than (slt) instructions.
Typology: Slides
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What are the truth tables?
What are the truth tables? Docsity.com
cin a b c (^) out s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
Give a Boolean formula for s
Give a Boolean formula for c (^) out
Design now a circuit using and, or, xor.
Suppose that each gate has a unit delay. What is the critical path (= path with the longest delay)? Docsity.com
Iterate the idea, generate and propagate
ci+1 = g (^) i + pici
= g (^) i + pi(g (^) i-1 + pi-1 ci-1 ) = gi + pig (^) i-1 + pipi-1 ci- = g (^) i + pig (^) i-1 + pipi-1 g (^) i-2 +…+ p (^) ipi-1 …p 1 g (^0) +pipi-1 …p 1 p 0 c 0
Two level AND-OR circuit
Carry is known early!
Fast because critical path is shorter O(log n) gate delays [assuming 2-input gates] More complex to implement Design is less regular Layout of one bit adder cells depend on i
couple blocks of carry lookahead adders
0
2
Result
Operation
a
1
CarryIn
CarryOut
0 1
Binvert
b
a31 0 Set
ALU0 Result
CarryIn
a
a1 0 Result
a2 0 Result
Operation
b
b
b
b
Result Overflow
Binvert
CarryIn
Less
CarryIn CarryOut
CarryInALU1Less CarryOut
CarryInALU2Less CarryOut
CarryInALU31Less
000 = and 001 = or 010 = add 110 = subtract 111 = slt
a0 Result
a1 Result 0
a2 Result 0
Operation
b
b
b
b
Result Overflow
Bnegate
Zero
CarryIn ALU0Less CarryOut
CarryInALU1Less CarryOut
CarryInALU2Less CarryOut
CarryInALU31Less